SPI_DEVICE/2P Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 12.813m 346.394ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.330s 24.596us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.800s 428.514us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 25.400s 4.169ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 15.750s 1.524ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.660s 589.129us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.800s 428.514us 20 20 100.00
spi_device_csr_aliasing 15.750s 1.524ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.670s 13.227us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.200s 413.775us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.880s 76.501us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.120s 86.208us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.750s 18.958us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 9.420s 770.482us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 9.420s 770.482us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 19.950s 31.392ms 50 50 100.00
spi_device_tpm_sts_read 1.000s 386.471us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 44.620s 8.021ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 38.850s 12.985ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 27.030s 110.440ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 27.030s 110.440ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 37.200s 8.000ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 37.200s 8.000ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 37.200s 8.000ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 37.200s 8.000ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 37.200s 8.000ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 30.790s 17.515ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 1.731m 18.716ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.731m 18.716ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.731m 18.716ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.134m 24.588ms 50 50 100.00
spi_device_read_buffer_direct 20.600s 1.950ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.731m 18.716ms 50 50 100.00
spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 quad_spi spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 dual_spi spi_device_flash_all 7.447m 253.489ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 44.770s 22.728ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 44.770s 22.728ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 12.813m 346.394ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 9.472m 337.553ms 50 50 100.00
V2 stress_all spi_device_stress_all 22.891m 553.134ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.770s 45.630us 50 50 100.00
V2 intr_test spi_device_intr_test 0.810s 15.889us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.430s 925.985us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.430s 925.985us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.330s 24.596us 5 5 100.00
spi_device_csr_rw 2.800s 428.514us 20 20 100.00
spi_device_csr_aliasing 15.750s 1.524ms 5 5 100.00
spi_device_same_csr_outstanding 4.300s 578.491us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.330s 24.596us 5 5 100.00
spi_device_csr_rw 2.800s 428.514us 20 20 100.00
spi_device_csr_aliasing 15.750s 1.524ms 5 5 100.00
spi_device_same_csr_outstanding 4.300s 578.491us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.220s 310.785us 5 5 100.00
spi_device_tl_intg_err 21.740s 829.199us 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 21.740s 829.199us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.95 98.35 94.20 98.61 89.36 97.14 95.81 98.17

Past Results