SPI_DEVICE/2P Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 10.993m 71.781ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.330s 121.020us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.620s 207.495us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 39.580s 17.994ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 20.740s 302.307us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.820s 56.334us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.620s 207.495us 20 20 100.00
spi_device_csr_aliasing 20.740s 302.307us 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.690s 11.121us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.150s 596.815us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.830s 90.489us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.100s 64.227us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.760s 72.700us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 9.260s 170.081us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 9.260s 170.081us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 22.340s 7.637ms 50 50 100.00
spi_device_tpm_sts_read 1.140s 2.215ms 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 38.370s 6.708ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 22.170s 30.622ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 33.240s 22.853ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 33.240s 22.853ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 36.240s 28.758ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 36.240s 28.758ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 36.240s 28.758ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 36.240s 28.758ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 36.240s 28.758ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 35.990s 9.484ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.563m 14.139ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.563m 14.139ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.563m 14.139ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 56.870s 49.621ms 50 50 100.00
spi_device_read_buffer_direct 20.410s 8.046ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.563m 14.139ms 50 50 100.00
spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 quad_spi spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 dual_spi spi_device_flash_all 7.664m 133.951ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 29.900s 36.963ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 29.900s 36.963ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 10.993m 71.781ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 12.204m 396.989ms 50 50 100.00
V2 stress_all spi_device_stress_all 11.616m 148.175ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.790s 41.208us 50 50 100.00
V2 intr_test spi_device_intr_test 0.770s 13.143us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.080s 233.439us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.080s 233.439us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.330s 121.020us 5 5 100.00
spi_device_csr_rw 2.620s 207.495us 20 20 100.00
spi_device_csr_aliasing 20.740s 302.307us 5 5 100.00
spi_device_same_csr_outstanding 4.200s 301.645us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.330s 121.020us 5 5 100.00
spi_device_csr_rw 2.620s 207.495us 20 20 100.00
spi_device_csr_aliasing 20.740s 302.307us 5 5 100.00
spi_device_same_csr_outstanding 4.200s 301.645us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.100s 116.225us 5 5 100.00
spi_device_tl_intg_err 24.920s 1.101ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 24.920s 1.101ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.93 98.35 94.20 98.61 89.36 97.14 95.81 98.07

Past Results