SPI_DEVICE/2P Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.379m	342.516ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.370s	41.372us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	488.122us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.740s	2.853ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.990s	4.388ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.090s	58.859us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	488.122us	20	20	100.00
		spi_device_csr_aliasing	22.990s	4.388ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	36.440us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.140s	101.178us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	203.346us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	57.784us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	35.472us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.000s	861.875us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.000s	861.875us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.520s	9.840ms	50	50	100.00
		spi_device_tpm_sts_read	1.020s	175.947us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.650s	10.735ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.950s	51.135ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.140s	13.215ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.140s	13.215ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.120s	2.844ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.120s	2.844ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.120s	2.844ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.120s	2.844ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.120s	2.844ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.980s	118.689ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.216m	19.550ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.216m	19.550ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.216m	19.550ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.056m	17.716ms	50	50	100.00
		spi_device_read_buffer_direct	21.850s	7.434ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.216m	19.550ms	50	50	100.00
		spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.408m	65.555ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.620s	2.008ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.620s	2.008ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.379m	342.516ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.025m	318.891ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.773m	421.110ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.820s	17.216us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	46.944us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.540s	423.270us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.540s	423.270us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.370s	41.372us	5	5	100.00
		spi_device_csr_rw	2.860s	488.122us	20	20	100.00
		spi_device_csr_aliasing	22.990s	4.388ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	370.749us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.370s	41.372us	5	5	100.00
		spi_device_csr_rw	2.860s	488.122us	20	20	100.00
		spi_device_csr_aliasing	22.990s	4.388ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	370.749us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.290s	171.627us	5	5	100.00
		spi_device_tl_intg_err	22.780s	1.023ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.780s	1.023ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1100	1101	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.92	98.34	94.20	98.61	89.36	97.12	95.81	98.02

Failure Buckets

• UVM_ERROR (spi_device_scoreboard.sv:1746) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:
  • Test spi_device_stress_all has 1 failures.

    • 47.spi_device_stress_all.113923790027042321902379849236265828704150857322385538813494436890198520872019
      Line 294, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest/run.log

        UVM_ERROR @ 144858032370 ps: (spi_device_scoreboard.sv:1746) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
        UVM_INFO @ 145780592370 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/12
        UVM_INFO @ 147544152370 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/10
        UVM_INFO @ 148809650370 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/12
        UVM_INFO @ 150802102370 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/12
      

Past Results

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