SPI_DEVICE/2P Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 11.954m 217.645ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.500s 144.279us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.760s 425.025us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 37.700s 1.957ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 24.130s 1.197ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.040s 176.089us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.760s 425.025us 20 20 100.00
spi_device_csr_aliasing 24.130s 1.197ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.720s 12.235us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.040s 23.005us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.850s 23.152us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.140s 32.647us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.710s 39.900us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 12.630s 1.327ms 50 50 100.00
V2 tpm_write spi_device_tpm_rw 12.630s 1.327ms 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 26.870s 8.847ms 50 50 100.00
spi_device_tpm_sts_read 1.150s 160.193us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 52.400s 10.161ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 40.260s 16.274ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 30.860s 10.708ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 30.860s 10.708ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 25.750s 11.558ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 25.750s 11.558ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 25.750s 11.558ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 25.750s 11.558ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 25.750s 11.558ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 47.200s 13.985ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.319m 82.776ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.319m 82.776ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.319m 82.776ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.078m 8.695ms 50 50 100.00
spi_device_read_buffer_direct 19.650s 2.722ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.319m 82.776ms 50 50 100.00
spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 quad_spi spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 dual_spi spi_device_flash_all 7.349m 219.080ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 21.430s 4.702ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 21.430s 4.702ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 11.954m 217.645ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 11.321m 103.317ms 50 50 100.00
V2 stress_all spi_device_stress_all 11.300m 261.609ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.770s 83.877us 50 50 100.00
V2 intr_test spi_device_intr_test 0.830s 14.862us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.670s 360.955us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.670s 360.955us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.500s 144.279us 5 5 100.00
spi_device_csr_rw 2.760s 425.025us 20 20 100.00
spi_device_csr_aliasing 24.130s 1.197ms 5 5 100.00
spi_device_same_csr_outstanding 4.290s 154.396us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.500s 144.279us 5 5 100.00
spi_device_csr_rw 2.760s 425.025us 20 20 100.00
spi_device_csr_aliasing 24.130s 1.197ms 5 5 100.00
spi_device_same_csr_outstanding 4.290s 154.396us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.110s 855.620us 5 5 100.00
spi_device_tl_intg_err 24.180s 2.076ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 24.180s 2.076ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.10 98.35 94.20 98.61 89.36 97.23 95.82 99.10

Past Results