SPI_DEVICE/2P Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 12.889m 182.786ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.420s 45.799us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.850s 716.358us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 41.350s 18.026ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 22.840s 20.483ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.300s 60.077us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.850s 716.358us 20 20 100.00
spi_device_csr_aliasing 22.840s 20.483ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.670s 12.955us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.070s 272.311us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.850s 54.697us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.110s 25.533us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.750s 49.826us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 7.910s 634.351us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 7.910s 634.351us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 23.710s 8.692ms 50 50 100.00
spi_device_tpm_sts_read 1.080s 139.486us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 45.600s 9.320ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 35.470s 41.696ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 29.000s 9.513ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 29.000s 9.513ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 37.680s 3.130ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 37.680s 3.130ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 37.680s 3.130ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 37.680s 3.130ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 37.680s 3.130ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 23.260s 94.355ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 1.744m 9.882ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.744m 9.882ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.744m 9.882ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 51.550s 8.762ms 50 50 100.00
spi_device_read_buffer_direct 15.830s 1.930ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.744m 9.882ms 50 50 100.00
spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 quad_spi spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 dual_spi spi_device_flash_all 8.564m 72.453ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 11.830s 6.030ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 11.830s 6.030ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 12.889m 182.786ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 11.662m 446.582ms 50 50 100.00
V2 stress_all spi_device_stress_all 16.457m 209.652ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.790s 18.426us 50 50 100.00
V2 intr_test spi_device_intr_test 0.820s 15.795us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.490s 937.904us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.490s 937.904us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.420s 45.799us 5 5 100.00
spi_device_csr_rw 2.850s 716.358us 20 20 100.00
spi_device_csr_aliasing 22.840s 20.483ms 5 5 100.00
spi_device_same_csr_outstanding 4.550s 1.022ms 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.420s 45.799us 5 5 100.00
spi_device_csr_rw 2.850s 716.358us 20 20 100.00
spi_device_csr_aliasing 22.840s 20.483ms 5 5 100.00
spi_device_same_csr_outstanding 4.550s 1.022ms 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.090s 250.208us 5 5 100.00
spi_device_tl_intg_err 20.630s 4.045ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 20.630s 4.045ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.11 98.35 94.21 98.61 89.36 97.23 95.82 99.15

Past Results