SPI_DEVICE/2P Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 13.455m 76.722ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.410s 41.810us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.610s 404.722us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 37.490s 7.208ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 15.480s 762.208us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.070s 165.478us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.610s 404.722us 20 20 100.00
spi_device_csr_aliasing 15.480s 762.208us 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.700s 12.191us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.140s 91.557us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.860s 58.738us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.160s 25.780us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.740s 45.642us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 10.900s 1.135ms 50 50 100.00
V2 tpm_write spi_device_tpm_rw 10.900s 1.135ms 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 25.320s 62.149ms 50 50 100.00
spi_device_tpm_sts_read 1.060s 207.367us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 48.260s 17.082ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 36.520s 12.845ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 27.650s 10.402ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 27.650s 10.402ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 26.950s 13.091ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 26.950s 13.091ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 26.950s 13.091ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 26.950s 13.091ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 26.950s 13.091ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 40.300s 12.004ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 3.483m 16.144ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 3.483m 16.144ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 3.483m 16.144ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.160m 5.464ms 50 50 100.00
spi_device_read_buffer_direct 24.270s 2.007ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 3.483m 16.144ms 50 50 100.00
spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 quad_spi spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 dual_spi spi_device_flash_all 9.534m 315.733ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 20.890s 2.593ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 20.890s 2.593ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 13.455m 76.722ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 10.355m 308.932ms 50 50 100.00
V2 stress_all spi_device_stress_all 15.632m 1.078s 50 50 100.00
V2 alert_test spi_device_alert_test 0.780s 51.491us 50 50 100.00
V2 intr_test spi_device_intr_test 0.810s 16.883us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.710s 446.115us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.710s 446.115us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.410s 41.810us 5 5 100.00
spi_device_csr_rw 2.610s 404.722us 20 20 100.00
spi_device_csr_aliasing 15.480s 762.208us 5 5 100.00
spi_device_same_csr_outstanding 4.060s 154.125us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.410s 41.810us 5 5 100.00
spi_device_csr_rw 2.610s 404.722us 20 20 100.00
spi_device_csr_aliasing 15.480s 762.208us 5 5 100.00
spi_device_same_csr_outstanding 4.060s 154.125us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.300s 116.941us 5 5 100.00
spi_device_tl_intg_err 22.880s 911.255us 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 22.880s 911.255us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.11 98.35 94.20 98.61 89.36 97.23 95.82 99.20

Past Results