SPI_DEVICE/2P Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.451m	66.570ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	73.972us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.750s	316.638us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.800s	11.222ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.870s	1.111ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.380s	60.129us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.750s	316.638us	20	20	100.00
		spi_device_csr_aliasing	23.870s	1.111ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	11.270us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	528.246us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	167.635us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	95.399us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	152.174us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.370s	797.572us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.370s	797.572us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.740s	27.605ms	50	50	100.00
		spi_device_tpm_sts_read	1.140s	170.597us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.250s	82.825ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	20.510s	6.249ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.500s	8.654ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.500s	8.654ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	24.970s	2.267ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	24.970s	2.267ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	24.970s	2.267ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	24.970s	2.267ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	24.970s	2.267ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	48.210s	12.515ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.178m	66.869ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.178m	66.869ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.178m	66.869ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.303m	24.359ms	50	50	100.00
		spi_device_read_buffer_direct	19.600s	6.401ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.178m	66.869ms	50	50	100.00
		spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	6.447m	221.658ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	34.120s	7.503ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	34.120s	7.503ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.451m	66.570ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.762m	140.023ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.330m	377.008ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	15.274us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	19.001us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.250s	161.557us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.250s	161.557us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	73.972us	5	5	100.00
		spi_device_csr_rw	2.750s	316.638us	20	20	100.00
		spi_device_csr_aliasing	23.870s	1.111ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	844.886us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	73.972us	5	5	100.00
		spi_device_csr_rw	2.750s	316.638us	20	20	100.00
		spi_device_csr_aliasing	23.870s	1.111ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	844.886us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.210s	174.055us	5	5	100.00
		spi_device_tl_intg_err	23.970s	5.532ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.970s	5.532ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1100	1101	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.12	98.36	94.20	98.61	89.36	97.24	95.82	99.25

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:667) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_all has 1 failures.

    • 30.spi_device_flash_all.67056622737780272765320506626895142789959720658313931147857998895612787756398
      Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest/run.log

        UVM_ERROR @ 8205808525 ps: (spi_device_pass_base_vseq.sv:667) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        UVM_INFO @ 8531313503 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/10
        UVM_INFO @ 9914394503 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/10
        UVM_INFO @ 10886688525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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