SPI_DEVICE/2P Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.716m	50.870ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	144.899us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.980s	183.694us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.920s	7.542ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.270s	3.467ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.030s	60.587us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.980s	183.694us	20	20	100.00
		spi_device_csr_aliasing	22.270s	3.467ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	47.254us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.960s	91.018us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	18.811us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	58.383us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	18.286us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.750s	454.376us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.750s	454.376us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.630s	8.315ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	473.220us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.650s	10.377ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.690s	25.999ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.720s	68.265ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.720s	68.265ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	35.160s	6.613ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	35.160s	6.613ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	35.160s	6.613ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	35.160s	6.613ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	35.160s	6.613ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	24.710s	11.133ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.466m	72.776ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.466m	72.776ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.466m	72.776ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.068m	9.327ms	50	50	100.00
		spi_device_read_buffer_direct	20.740s	5.269ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.466m	72.776ms	50	50	100.00
		spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.412m	210.435ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.790s	4.570ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.790s	4.570ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.716m	50.870ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.619m	186.847ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.299m	293.479ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	12.248us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	35.623us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.520s	85.694us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.520s	85.694us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	144.899us	5	5	100.00
		spi_device_csr_rw	2.980s	183.694us	20	20	100.00
		spi_device_csr_aliasing	22.270s	3.467ms	5	5	100.00
		spi_device_same_csr_outstanding	4.560s	628.654us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	144.899us	5	5	100.00
		spi_device_csr_rw	2.980s	183.694us	20	20	100.00
		spi_device_csr_aliasing	22.270s	3.467ms	5	5	100.00
		spi_device_same_csr_outstanding	4.560s	628.654us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.190s	370.364us	5	5	100.00
		spi_device_tl_intg_err	22.680s	1.954ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.680s	1.954ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.11	98.35	94.21	98.61	89.36	97.23	95.82	99.20

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