SPI_DEVICE/2P Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 9.233m 53.288ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.470s 76.969us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.880s 127.428us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 37.090s 25.883ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 24.430s 5.201ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.450s 93.160us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.880s 127.428us 20 20 100.00
spi_device_csr_aliasing 24.430s 5.201ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.730s 18.363us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.210s 124.553us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.860s 72.283us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.180s 90.066us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.720s 36.585us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 6.100s 249.112us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 6.100s 249.112us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 25.680s 124.182ms 50 50 100.00
spi_device_tpm_sts_read 1.050s 101.109us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 49.690s 9.303ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 45.270s 29.572ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 29.430s 11.221ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 29.430s 11.221ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 40.090s 4.257ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 40.090s 4.257ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 40.090s 4.257ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 40.090s 4.257ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 40.090s 4.257ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 30.660s 18.244ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.116m 57.908ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.116m 57.908ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.116m 57.908ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 37.420s 10.118ms 50 50 100.00
spi_device_read_buffer_direct 22.980s 4.548ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.116m 57.908ms 50 50 100.00
spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 quad_spi spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 dual_spi spi_device_flash_all 9.851m 86.490ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 29.730s 11.914ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 29.730s 11.914ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 9.233m 53.288ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 10.621m 63.028ms 50 50 100.00
V2 stress_all spi_device_stress_all 17.172m 129.397ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.820s 30.258us 50 50 100.00
V2 intr_test spi_device_intr_test 0.790s 16.186us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.200s 221.247us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.200s 221.247us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.470s 76.969us 5 5 100.00
spi_device_csr_rw 2.880s 127.428us 20 20 100.00
spi_device_csr_aliasing 24.430s 5.201ms 5 5 100.00
spi_device_same_csr_outstanding 4.690s 4.253ms 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.470s 76.969us 5 5 100.00
spi_device_csr_rw 2.880s 127.428us 20 20 100.00
spi_device_csr_aliasing 24.430s 5.201ms 5 5 100.00
spi_device_same_csr_outstanding 4.690s 4.253ms 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.100s 61.921us 5 5 100.00
spi_device_tl_intg_err 24.380s 5.558ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 24.380s 5.558ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.10 98.35 94.20 98.61 89.36 97.23 95.82 99.15

Past Results