SPI_DEVICE/2P Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 16.145m 99.407ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.380s 151.739us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.880s 478.502us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 35.140s 972.521us 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 24.920s 4.495ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.870s 421.226us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.880s 478.502us 20 20 100.00
spi_device_csr_aliasing 24.920s 4.495ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.670s 11.466us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.180s 334.063us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.870s 58.576us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.140s 358.074us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.720s 36.677us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 8.750s 922.091us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 8.750s 922.091us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 28.640s 10.466ms 50 50 100.00
spi_device_tpm_sts_read 1.230s 165.984us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.069m 11.897ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 31.120s 9.855ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 30.900s 47.503ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 30.900s 47.503ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 41.980s 4.541ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 41.980s 4.541ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 41.980s 4.541ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 41.980s 4.541ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 41.980s 4.541ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 37.420s 47.297ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.108m 21.679ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.108m 21.679ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.108m 21.679ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.218m 20.002ms 50 50 100.00
spi_device_read_buffer_direct 18.680s 1.287ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.108m 21.679ms 50 50 100.00
spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 quad_spi spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 dual_spi spi_device_flash_all 7.636m 236.592ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 22.120s 2.226ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 22.120s 2.226ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 16.145m 99.407ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 10.771m 259.196ms 50 50 100.00
V2 stress_all spi_device_stress_all 21.720m 530.484ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.790s 15.243us 50 50 100.00
V2 intr_test spi_device_intr_test 0.830s 12.780us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.460s 894.960us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.460s 894.960us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.380s 151.739us 5 5 100.00
spi_device_csr_rw 2.880s 478.502us 20 20 100.00
spi_device_csr_aliasing 24.920s 4.495ms 5 5 100.00
spi_device_same_csr_outstanding 4.680s 227.749us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.380s 151.739us 5 5 100.00
spi_device_csr_rw 2.880s 478.502us 20 20 100.00
spi_device_csr_aliasing 24.920s 4.495ms 5 5 100.00
spi_device_same_csr_outstanding 4.680s 227.749us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.160s 378.281us 5 5 100.00
spi_device_tl_intg_err 23.740s 2.066ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 23.740s 2.066ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.10 98.35 94.20 98.61 89.36 97.23 95.82 99.15

Past Results