SPI_DEVICE/2P Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.181m	87.700ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.490s	160.283us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.810s	97.836us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.940s	10.044ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.460s	5.946ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.990s	441.695us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.810s	97.836us	20	20	100.00
		spi_device_csr_aliasing	23.460s	5.946ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	16.758us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.220s	298.895us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.900s	20.585us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.170s	61.330us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	30.644us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.780s	405.765us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.780s	405.765us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.000s	43.138ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	123.931us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.470s	10.681ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	50.330s	36.615ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.490s	33.360ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.490s	33.360ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.520s	38.323ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.520s	38.323ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.520s	38.323ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.520s	38.323ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.520s	38.323ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	49.450s	52.753ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.554m	186.798ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.554m	186.798ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.554m	186.798ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.145m	4.877ms	50	50	100.00
		spi_device_read_buffer_direct	23.360s	2.241ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.554m	186.798ms	50	50	100.00
		spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.621m	551.786ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.680s	5.913ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.680s	5.913ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.181m	87.700ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.676m	56.462ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.691m	82.405ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	54.260us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	72.657us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.510s	66.709us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.510s	66.709us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.490s	160.283us	5	5	100.00
		spi_device_csr_rw	2.810s	97.836us	20	20	100.00
		spi_device_csr_aliasing	23.460s	5.946ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	231.503us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.490s	160.283us	5	5	100.00
		spi_device_csr_rw	2.810s	97.836us	20	20	100.00
		spi_device_csr_aliasing	23.460s	5.946ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	231.503us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.200s	93.128us	5	5	100.00
		spi_device_tl_intg_err	22.000s	4.049ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.000s	4.049ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.11	98.35	94.19	98.61	89.36	97.23	95.82	99.20

Past Results

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