SPI_DEVICE/2P Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.675m	77.019ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.490s	462.706us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.750s	196.153us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.010s	2.438ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.220s	610.266us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.760s	106.845us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.750s	196.153us	20	20	100.00
		spi_device_csr_aliasing	22.220s	610.266us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	18.179us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.010s	97.415us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.900s	52.398us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.170s	29.207us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	17.191us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.120s	1.942ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.120s	1.942ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.570s	29.817ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	393.484us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.380s	41.866ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.840s	16.578ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	24.540s	34.034ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	24.540s	34.034ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.800s	5.943ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.800s	5.943ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.800s	5.943ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.800s	5.943ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.800s	5.943ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.390s	16.025ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.971m	11.334ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.971m	11.334ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.971m	11.334ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	43.050s	16.188ms	50	50	100.00
		spi_device_read_buffer_direct	17.690s	4.561ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.971m	11.334ms	50	50	100.00
		spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.071m	113.043ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	36.190s	15.961ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	36.190s	15.961ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.675m	77.019ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.821m	75.409ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.735m	111.268ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.780s	13.242us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	17.029us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.950s	500.374us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.950s	500.374us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.490s	462.706us	5	5	100.00
		spi_device_csr_rw	2.750s	196.153us	20	20	100.00
		spi_device_csr_aliasing	22.220s	610.266us	5	5	100.00
		spi_device_same_csr_outstanding	4.150s	721.120us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.490s	462.706us	5	5	100.00
		spi_device_csr_rw	2.750s	196.153us	20	20	100.00
		spi_device_csr_aliasing	22.220s	610.266us	5	5	100.00
		spi_device_same_csr_outstanding	4.150s	721.120us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.220s	505.382us	5	5	100.00
		spi_device_tl_intg_err	23.180s	1.680ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.180s	1.680ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1100	1101	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	98.35	94.20	98.61	89.36	97.23	95.82	99.15

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:896) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*])

has 1 failures:

Test spi_device_stress_all has 1 failures.

45.spi_device_stress_all.39455832545538999351493319290340529395252559290204763854352968163504657052098
Line 290, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 192409804442 ps: (spi_device_scoreboard.sv:896) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_FATAL @ 192409804443 ps: (spi_device_scoreboard.sv:859) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 192409804443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---