SPI_DEVICE/2P Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.120m	744.150ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.490s	81.791us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.770s	115.549us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	43.810s	2.826ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.860s	318.430us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.440s	59.518us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.770s	115.549us	20	20	100.00
		spi_device_csr_aliasing	21.860s	318.430us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	12.786us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.720s	61.403us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.890s	21.530us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.170s	34.863us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	19.657us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.310s	151.358us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.310s	151.358us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.530s	41.429ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	394.484us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.160s	70.730ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.840s	185.112ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	21.470s	21.684ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	21.470s	21.684ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.360s	2.513ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.360s	2.513ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.360s	2.513ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.360s	2.513ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.360s	2.513ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	28.780s	8.550ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.449m	53.465ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.449m	53.465ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.449m	53.465ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.230s	4.228ms	50	50	100.00
		spi_device_read_buffer_direct	18.550s	1.892ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.449m	53.465ms	50	50	100.00
		spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.579m	310.546ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.890s	11.696ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	25.890s	11.696ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.120m	744.150ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.806m	79.308ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.777m	127.838ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.830s	15.652us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.900s	17.907us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.830s	154.536us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.830s	154.536us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.490s	81.791us	5	5	100.00
		spi_device_csr_rw	2.770s	115.549us	20	20	100.00
		spi_device_csr_aliasing	21.860s	318.430us	5	5	100.00
		spi_device_same_csr_outstanding	4.230s	62.050us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.490s	81.791us	5	5	100.00
		spi_device_csr_rw	2.770s	115.549us	20	20	100.00
		spi_device_csr_aliasing	21.860s	318.430us	5	5	100.00
		spi_device_same_csr_outstanding	4.230s	62.050us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.540s	621.118us	5	5	100.00
		spi_device_tl_intg_err	24.600s	3.423ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.600s	3.423ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1100	1101	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.35	94.02	98.62	89.36	97.23	95.43	99.25

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1830) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}}

has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

13.spi_device_cfg_cmd.80936085971883505763520509466220261976984722721375212663564383985752829933642
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 310617348 ps: (spi_device_scoreboard.sv:1830) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4ef96) != exp '{'{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h13be5, wel:'h0, busy:'h0}, '{other_status:'h13be5, wel:'h0, busy:'h0}}
  UVM_ERROR @ 311367348 ps: (spi_device_scoreboard.sv:1830) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4ef96) != exp '{'{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h13be5, wel:'h0, busy:'h0}, '{other_status:'h13be5, wel:'h0, busy:'h0}}
  UVM_INFO @ 326992348 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xe9
  UVM_INFO @ 353617348 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0x4
  UVM_INFO @ 10524867348 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0x6