SPI_DEVICE/2P Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.614m	241.702ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	186.863us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.180s	123.061us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.110s	8.201ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.040s	620.066us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.900s	465.480us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.180s	123.061us	20	20	100.00
		spi_device_csr_aliasing	16.040s	620.066us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	10.292us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.100s	161.299us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	41.493us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	27.822us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	35.803us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.770s	239.053us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.770s	239.053us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.090s	14.010ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	141.699us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.810s	9.670ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.840s	28.578ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.530s	36.364ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.530s	36.364ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.130s	10.559ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.130s	10.559ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.130s	10.559ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.130s	10.559ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.130s	10.559ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	39.360s	13.540ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.528m	30.849ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.528m	30.849ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.528m	30.849ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.640s	12.072ms	50	50	100.00
		spi_device_read_buffer_direct	26.630s	2.036ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.528m	30.849ms	50	50	100.00
		spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.987m	285.758ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.030s	5.097ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	20.030s	5.097ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.614m	241.702ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.350m	276.308ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.366m	240.566ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	13.783us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	16.232us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.270s	696.581us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.270s	696.581us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	186.863us	5	5	100.00
		spi_device_csr_rw	3.180s	123.061us	20	20	100.00
		spi_device_csr_aliasing	16.040s	620.066us	5	5	100.00
		spi_device_same_csr_outstanding	4.980s	422.614us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	186.863us	5	5	100.00
		spi_device_csr_rw	3.180s	123.061us	20	20	100.00
		spi_device_csr_aliasing	16.040s	620.066us	5	5	100.00
		spi_device_same_csr_outstanding	4.980s	422.614us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.200s	443.888us	5	5	100.00
		spi_device_tl_intg_err	23.330s	12.476ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.330s	12.476ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.35	94.02	98.62	89.36	97.23	95.43	99.20

Past Results

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