SPI_DEVICE/2P Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.182m	333.190ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	38.287us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.650s	40.148us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.660s	27.047ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.030s	2.180ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.210s	307.268us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.650s	40.148us	20	20	100.00
		spi_device_csr_aliasing	23.030s	2.180ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	10.501us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.710s	80.541us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	50.005us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	33.289us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	38.574us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.730s	265.214us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.730s	265.214us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.880s	7.632ms	50	50	100.00
		spi_device_tpm_sts_read	1.030s	225.202us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.820s	9.455ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.980s	39.571ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	19.390s	5.830ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	19.390s	5.830ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.040s	7.846ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.040s	7.846ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.040s	7.846ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.040s	7.846ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.040s	7.846ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.370s	11.983ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.995m	59.310ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.995m	59.310ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.995m	59.310ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.140s	4.167ms	50	50	100.00
		spi_device_read_buffer_direct	22.760s	7.937ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.995m	59.310ms	50	50	100.00
		spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.283m	56.476ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.670s	35.336ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.670s	35.336ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.182m	333.190ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.401m	72.040ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.651m	810.376ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	42.291us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.870s	14.841us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.810s	198.007us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.810s	198.007us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	38.287us	5	5	100.00
		spi_device_csr_rw	2.650s	40.148us	20	20	100.00
		spi_device_csr_aliasing	23.030s	2.180ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	661.204us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	38.287us	5	5	100.00
		spi_device_csr_rw	2.650s	40.148us	20	20	100.00
		spi_device_csr_aliasing	23.030s	2.180ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	661.204us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.240s	971.355us	5	5	100.00
		spi_device_tl_intg_err	21.510s	809.093us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.510s	809.093us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.02	98.35	94.02	98.62	89.36	97.23	95.43	99.10

Past Results

• Latest
• 2024.06.12_05.03.50
• 2024.06.11_12.04.47
• 2024.06.10_06.55.09
• 2024.06.08_13.18.12
• 2024.06.07_05.01.55
• 2024.06.06_11.12.22
• 2024.06.05_04.07.11