SPI_DEVICE/2P Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.233m	79.532ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	73.721us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.690s	425.648us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.990s	14.173ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.930s	597.930us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.190s	59.334us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.690s	425.648us	20	20	100.00
		spi_device_csr_aliasing	19.930s	597.930us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	22.272us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	58.961us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	14.832us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.190s	135.978us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	22.874us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.290s	501.039us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.290s	501.039us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.520s	8.483ms	50	50	100.00
		spi_device_tpm_sts_read	1.090s	111.498us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.640s	23.825ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	44.250s	19.391ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	48.730s	39.456ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	48.730s	39.456ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.340s	24.454ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.340s	24.454ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.340s	24.454ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.340s	24.454ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.340s	24.454ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.140s	9.385ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.825m	14.032ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.825m	14.032ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.825m	14.032ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.151m	5.725ms	50	50	100.00
		spi_device_read_buffer_direct	20.510s	6.969ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.825m	14.032ms	50	50	100.00
		spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.327m	293.693ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.720s	2.876ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.720s	2.876ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.233m	79.532ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.443m	71.565ms	50	50	100.00
V2	stress_all	spi_device_stress_all	24.075m	162.027ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.830s	41.662us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	117.862us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.880s	291.686us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.880s	291.686us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	73.721us	5	5	100.00
		spi_device_csr_rw	2.690s	425.648us	20	20	100.00
		spi_device_csr_aliasing	19.930s	597.930us	5	5	100.00
		spi_device_same_csr_outstanding	4.450s	216.742us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	73.721us	5	5	100.00
		spi_device_csr_rw	2.690s	425.648us	20	20	100.00
		spi_device_csr_aliasing	19.930s	597.930us	5	5	100.00
		spi_device_same_csr_outstanding	4.450s	216.742us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.100s	264.615us	5	5	100.00
		spi_device_tl_intg_err	22.330s	3.277ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.330s	3.277ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.20

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