SPI_DEVICE/2P Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.571m	337.934ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	48.451us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.760s	113.016us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.230s	9.375ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.380s	4.144ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.930s	174.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.760s	113.016us	20	20	100.00
		spi_device_csr_aliasing	22.380s	4.144ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	12.063us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.910s	176.986us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.890s	14.673us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	28.549us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	43.971us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.950s	860.360us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.950s	860.360us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.070s	18.936ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	246.854us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.380s	12.409ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	21.840s	7.974ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.440s	57.985ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.440s	57.985ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.630s	8.643ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.630s	8.643ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.630s	8.643ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.630s	8.643ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.630s	8.643ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.390s	44.682ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.194m	12.343ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.194m	12.343ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.194m	12.343ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.259m	36.289ms	50	50	100.00
		spi_device_read_buffer_direct	22.260s	2.137ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.194m	12.343ms	50	50	100.00
		spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.396m	203.441ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.050s	16.408ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.050s	16.408ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.571m	337.934ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.475m	227.207ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.206m	84.354ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	74.392us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	225.354us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.640s	1.496ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.640s	1.496ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	48.451us	5	5	100.00
		spi_device_csr_rw	2.760s	113.016us	20	20	100.00
		spi_device_csr_aliasing	22.380s	4.144ms	5	5	100.00
		spi_device_same_csr_outstanding	4.250s	196.997us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	48.451us	5	5	100.00
		spi_device_csr_rw	2.760s	113.016us	20	20	100.00
		spi_device_csr_aliasing	22.380s	4.144ms	5	5	100.00
		spi_device_same_csr_outstanding	4.250s	196.997us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.150s	86.807us	5	5	100.00
		spi_device_tl_intg_err	22.690s	906.950us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.690s	906.950us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.10	98.62	89.36	97.28	95.43	99.25

Past Results

• Latest
• 2024.06.22_11.44.59
• 2024.06.14_07.28.24
• 2024.06.12_05.03.50
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