SPI_DEVICE/2P Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 12.992m 84.689ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.410s 40.379us 5 5 100.00
V1 csr_rw spi_device_csr_rw 3.010s 231.641us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 33.510s 548.083us 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 22.370s 4.120ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.150s 110.678us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 3.010s 231.641us 20 20 100.00
spi_device_csr_aliasing 22.370s 4.120ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.680s 28.460us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.040s 83.618us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.870s 51.268us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.100s 33.431us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.730s 70.052us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 10.180s 853.769us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 10.180s 853.769us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 20.280s 7.960ms 50 50 100.00
spi_device_tpm_sts_read 1.040s 110.276us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.054m 12.224ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 44.340s 17.649ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 22.450s 7.150ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 22.450s 7.150ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 46.960s 90.783ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 46.960s 90.783ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 46.960s 90.783ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 46.960s 90.783ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 46.960s 90.783ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 25.950s 9.968ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.686m 71.325ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.686m 71.325ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.686m 71.325ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 59.210s 8.977ms 50 50 100.00
spi_device_read_buffer_direct 20.420s 2.585ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.686m 71.325ms 50 50 100.00
spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 quad_spi spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 dual_spi spi_device_flash_all 8.344m 70.388ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 22.320s 11.478ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 22.320s 11.478ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 12.992m 84.689ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 13.200m 86.530ms 50 50 100.00
V2 stress_all spi_device_stress_all 15.680m 118.089ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.830s 12.994us 50 50 100.00
V2 intr_test spi_device_intr_test 0.820s 118.418us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.990s 224.776us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.990s 224.776us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.410s 40.379us 5 5 100.00
spi_device_csr_rw 3.010s 231.641us 20 20 100.00
spi_device_csr_aliasing 22.370s 4.120ms 5 5 100.00
spi_device_same_csr_outstanding 4.190s 310.773us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.410s 40.379us 5 5 100.00
spi_device_csr_rw 3.010s 231.641us 20 20 100.00
spi_device_csr_aliasing 22.370s 4.120ms 5 5 100.00
spi_device_same_csr_outstanding 4.190s 310.773us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.190s 120.386us 5 5 100.00
spi_device_tl_intg_err 22.660s 6.733ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 22.660s 6.733ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.06 98.44 94.07 98.62 89.36 97.28 95.43 99.25

Past Results