SPI_DEVICE/2P Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.914m	187.172ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.360s	163.525us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.950s	456.343us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.450s	1.043ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.240s	1.285ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.300s	108.516us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.950s	456.343us	20	20	100.00
		spi_device_csr_aliasing	24.240s	1.285ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	11.044us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.410s	290.068us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	19.385us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	102.765us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	29.589us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.400s	210.641us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.400s	210.641us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.620s	9.248ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	217.614us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.920s	36.093ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.730s	26.274ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.340s	48.369ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.340s	48.369ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.280s	15.627ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.280s	15.627ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.280s	15.627ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.280s	15.627ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.280s	15.627ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.820s	39.665ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.643m	39.061ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.643m	39.061ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.643m	39.061ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	44.590s	5.338ms	50	50	100.00
		spi_device_read_buffer_direct	18.280s	1.659ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.643m	39.061ms	50	50	100.00
		spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.888m	64.780ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.830s	2.417ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	25.830s	2.417ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.914m	187.172ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.689m	60.696ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.407m	395.418ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	45.315us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	15.892us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.900s	2.857ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.900s	2.857ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.360s	163.525us	5	5	100.00
		spi_device_csr_rw	2.950s	456.343us	20	20	100.00
		spi_device_csr_aliasing	24.240s	1.285ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	210.707us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.360s	163.525us	5	5	100.00
		spi_device_csr_rw	2.950s	456.343us	20	20	100.00
		spi_device_csr_aliasing	24.240s	1.285ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	210.707us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.090s	169.332us	5	5	100.00
		spi_device_tl_intg_err	23.150s	2.055ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.150s	2.055ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1100	1101	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.20

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:2089) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}}

has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

18.spi_device_cfg_cmd.56146459234722430628055064137424558044458775528608747658334004820349766773642
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  24464185 ps: (spi_device_scoreboard.sv:2089) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc28146) != exp '{'{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}}
  UVM_ERROR @  25110649 ps: (spi_device_scoreboard.sv:2089) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc28146) != exp '{'{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}}
  UVM_ERROR @  25221760 ps: (spi_device_scoreboard.sv:2089) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc28146) != exp '{'{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}}
  UVM_ERROR @  25332871 ps: (spi_device_scoreboard.sv:2089) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc28146) != exp '{'{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}}
  UVM_ERROR @  25433881 ps: (spi_device_scoreboard.sv:2089) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc28146) != exp '{'{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h0, wel:'h1, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}, '{other_status:'h30a051, wel:'h0, busy:'h0}}