SPI_DEVICE/2P Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.937m	85.367ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	22.464us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.130s	129.011us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.440s	2.412ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.260s	1.618ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.330s	179.405us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.130s	129.011us	20	20	100.00
		spi_device_csr_aliasing	17.260s	1.618ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	13.334us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.850s	194.795us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	14.823us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	29.740us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	18.121us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.660s	956.736us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.660s	956.736us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.950s	33.878ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	152.729us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.790s	7.220ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.600s	249.116ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.640s	111.939ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.640s	111.939ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	32.090s	2.956ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	32.090s	2.956ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	32.090s	2.956ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	32.090s	2.956ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	32.090s	2.956ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	58.770s	72.194ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.010m	20.512ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.010m	20.512ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.010m	20.512ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.425m	11.936ms	50	50	100.00
		spi_device_read_buffer_direct	16.460s	3.834ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.010m	20.512ms	50	50	100.00
		spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.831m	309.985ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	34.460s	20.173ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	34.460s	20.173ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.937m	85.367ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.030m	324.103ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.587m	100.393ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.830s	13.364us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.870s	58.955us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.500s	768.221us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.500s	768.221us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	22.464us	5	5	100.00
		spi_device_csr_rw	3.130s	129.011us	20	20	100.00
		spi_device_csr_aliasing	17.260s	1.618ms	5	5	100.00
		spi_device_same_csr_outstanding	4.510s	206.877us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	22.464us	5	5	100.00
		spi_device_csr_rw	3.130s	129.011us	20	20	100.00
		spi_device_csr_aliasing	17.260s	1.618ms	5	5	100.00
		spi_device_same_csr_outstanding	4.510s	206.877us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.220s	219.156us	5	5	100.00
		spi_device_tl_intg_err	23.990s	1.057ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.990s	1.057ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.07	98.62	89.36	97.28	95.43	99.25

Past Results

• Latest
• 2024.06.25_11.43.52
• 2024.06.24_08.41.58
• 2024.06.23_08.04.38
• 2024.06.22_11.44.59
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• 2024.06.12_05.03.50
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