SPI_DEVICE/2P Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.138m	238.686ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.510s	181.786us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.140s	199.452us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.640s	3.763ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.660s	913.723us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.260s	672.155us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.140s	199.452us	20	20	100.00
		spi_device_csr_aliasing	24.660s	913.723us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	13.052us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.160s	184.946us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	12.829us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	119.265us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	43.500us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.210s	663.495us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.210s	663.495us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.370s	28.746ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	113.828us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	56.900s	10.854ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.600s	12.321ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.960s	20.650ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.960s	20.650ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	35.940s	13.941ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	35.940s	13.941ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	35.940s	13.941ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	35.940s	13.941ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	35.940s	13.941ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.350s	20.946ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.680m	31.738ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.680m	31.738ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.680m	31.738ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.326m	23.542ms	50	50	100.00
		spi_device_read_buffer_direct	17.070s	2.348ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.680m	31.738ms	50	50	100.00
		spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.981m	84.870ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.250s	20.890ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.250s	20.890ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.138m	238.686ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.864m	224.015ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.464m	571.376ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.840s	47.160us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	196.117us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.890s	768.972us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.890s	768.972us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.510s	181.786us	5	5	100.00
		spi_device_csr_rw	3.140s	199.452us	20	20	100.00
		spi_device_csr_aliasing	24.660s	913.723us	5	5	100.00
		spi_device_same_csr_outstanding	4.530s	601.664us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.510s	181.786us	5	5	100.00
		spi_device_csr_rw	3.140s	199.452us	20	20	100.00
		spi_device_csr_aliasing	24.660s	913.723us	5	5	100.00
		spi_device_same_csr_outstanding	4.530s	601.664us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.230s	339.853us	5	5	100.00
		spi_device_tl_intg_err	24.200s	4.319ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.200s	4.319ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1101	1101	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.07	98.62	89.36	97.29	95.43	99.25

Past Results

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