SPI_DEVICE/2P Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.836m	56.972ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	179.506us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	93.607us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.540s	524.468us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.100s	319.046us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.890s	279.228us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	93.607us	20	20	100.00
		spi_device_csr_aliasing	22.100s	319.046us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	12.504us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.120s	57.832us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	30.868us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	189.735us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	157.310us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.230s	324.970us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.230s	324.970us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.620s	15.929ms	50	50	100.00
		spi_device_tpm_sts_read	1.130s	79.922us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	41.270s	33.149ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.520s	55.381ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.490s	32.915ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.490s	32.915ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	32.450s	3.268ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	32.450s	3.268ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	32.450s	3.268ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	32.450s	3.268ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	32.450s	3.268ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.570s	15.517ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.987m	14.111ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.987m	14.111ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.987m	14.111ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.076m	5.179ms	50	50	100.00
		spi_device_read_buffer_direct	26.570s	8.068ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.987m	14.111ms	50	50	100.00
		spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.213m	301.550ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.150s	2.709ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.150s	2.709ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.836m	56.972ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.226m	68.742ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.907m	173.678ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	14.985us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	59.049us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.180s	281.431us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.180s	281.431us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	179.506us	5	5	100.00
		spi_device_csr_rw	2.840s	93.607us	20	20	100.00
		spi_device_csr_aliasing	22.100s	319.046us	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	163.107us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	179.506us	5	5	100.00
		spi_device_csr_rw	2.840s	93.607us	20	20	100.00
		spi_device_csr_aliasing	22.100s	319.046us	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	163.107us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.250s	110.799us	5	5	100.00
		spi_device_tl_intg_err	25.540s	1.104ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.540s	1.104ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	32.071m	1.500s	48	50	96.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.29	95.43	99.26

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test spi_device_flash_mode_ignore_cmds has 2 failures.

    • 34.spi_device_flash_mode_ignore_cmds.19247578806076914326997727769227331092227731720694534940835813755611358635020
      Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.spi_device_flash_mode_ignore_cmds.20223693045504387256766192453357645785771828355360484561899158919254870943385
      Line 309, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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