SPI_DEVICE/2P Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.848m	256.968ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.480s	45.946us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.810s	1.294ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.070s	2.467ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.500s	319.032us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.250s	58.097us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.810s	1.294ms	20	20	100.00
		spi_device_csr_aliasing	20.500s	319.032us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.740s	13.174us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.170s	55.691us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	46.794us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	130.692us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	50.556us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.400s	1.013ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.400s	1.013ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.180s	11.630ms	50	50	100.00
		spi_device_tpm_sts_read	1.100s	118.754us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.750s	40.167ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.660s	13.429ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.340s	37.386ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.340s	37.386ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.360s	3.143ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.360s	3.143ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.360s	3.143ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.360s	3.143ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.360s	3.143ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	21.600s	4.165ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.330m	14.587ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.330m	14.587ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.330m	14.587ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	53.200s	13.214ms	50	50	100.00
		spi_device_read_buffer_direct	21.000s	2.000ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.330m	14.587ms	50	50	100.00
		spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.939m	280.528ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.330s	3.278ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.330s	3.278ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.848m	256.968ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.427m	314.526ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.574m	175.354ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	48.754us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	12.766us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.870s	239.307us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.870s	239.307us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.480s	45.946us	5	5	100.00
		spi_device_csr_rw	2.810s	1.294ms	20	20	100.00
		spi_device_csr_aliasing	20.500s	319.032us	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	1.314ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.480s	45.946us	5	5	100.00
		spi_device_csr_rw	2.810s	1.294ms	20	20	100.00
		spi_device_csr_aliasing	20.500s	319.032us	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	1.314ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.200s	252.635us	5	5	100.00
		spi_device_tl_intg_err	24.800s	4.380ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.800s	4.380ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.721m	60.018ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Past Results

• Latest
• 2024.06.28_12.06.37
• 2024.06.27_11.23.46
• 2024.06.26_11.21.06
• 2024.06.25_11.43.52
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