SPI_DEVICE/2P Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.467m	273.219ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.310s	63.310us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	187.730us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.830s	541.967us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.620s	4.480ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.970s	271.353us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	187.730us	20	20	100.00
		spi_device_csr_aliasing	22.620s	4.480ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	30.527us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.250s	283.098us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	37.768us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	124.714us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	27.780us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.170s	536.540us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.170s	536.540us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	18.850s	14.847ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	136.963us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.970s	8.457ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.640s	49.753ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	35.030s	26.412ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	35.030s	26.412ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.720s	3.964ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.720s	3.964ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.720s	3.964ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.720s	3.964ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.720s	3.964ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.830s	17.587ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.780m	215.431ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.780m	215.431ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.780m	215.431ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.190m	17.169ms	50	50	100.00
		spi_device_read_buffer_direct	24.400s	25.649ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.780m	215.431ms	50	50	100.00
		spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.388m	285.675ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.310s	4.998ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.310s	4.998ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.467m	273.219ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.974m	236.147ms	50	50	100.00
V2	stress_all	spi_device_stress_all	25.817m	754.709ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	59.072us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	222.710us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.550s	861.029us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.550s	861.029us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.310s	63.310us	5	5	100.00
		spi_device_csr_rw	2.790s	187.730us	20	20	100.00
		spi_device_csr_aliasing	22.620s	4.480ms	5	5	100.00
		spi_device_same_csr_outstanding	4.780s	324.241us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.310s	63.310us	5	5	100.00
		spi_device_csr_rw	2.790s	187.730us	20	20	100.00
		spi_device_csr_aliasing	22.620s	4.480ms	5	5	100.00
		spi_device_same_csr_outstanding	4.780s	324.241us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.070s	269.555us	5	5	100.00
		spi_device_tl_intg_err	25.120s	2.182ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.120s	2.182ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.598m	236.146ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

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