SPI_DEVICE/2P Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.187m	81.113ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.370s	44.186us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.810s	1.406ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.410s	3.070ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.680s	4.297ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.940s	592.251us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.810s	1.406ms	20	20	100.00
		spi_device_csr_aliasing	25.680s	4.297ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	23.345us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.510s	82.253us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.910s	17.590us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	52.972us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	24.552us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.420s	215.395us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.420s	215.395us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.450s	38.596ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	108.371us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.106m	27.916ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	23.360s	7.360ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.070s	68.955ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.070s	68.955ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.960s	19.730ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.960s	19.730ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.960s	19.730ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.960s	19.730ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.960s	19.730ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	45.920s	65.244ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.115m	12.350ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.115m	12.350ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.115m	12.350ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	54.930s	3.721ms	50	50	100.00
		spi_device_read_buffer_direct	23.760s	1.533ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.115m	12.350ms	50	50	100.00
		spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.964m	65.463ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.550s	13.174ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.550s	13.174ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.187m	81.113ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.053m	47.845ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.900m	202.625ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	22.644us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	46.734us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.630s	385.802us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.630s	385.802us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.370s	44.186us	5	5	100.00
		spi_device_csr_rw	2.810s	1.406ms	20	20	100.00
		spi_device_csr_aliasing	25.680s	4.297ms	5	5	100.00
		spi_device_same_csr_outstanding	4.560s	160.044us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.370s	44.186us	5	5	100.00
		spi_device_csr_rw	2.810s	1.406ms	20	20	100.00
		spi_device_csr_aliasing	25.680s	4.297ms	5	5	100.00
		spi_device_same_csr_outstanding	4.560s	160.044us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.250s	93.393us	5	5	100.00
		spi_device_tl_intg_err	25.710s	8.584ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.710s	8.584ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.315m	47.274ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.06.30_11.26.58
• 2024.06.29_09.49.49
• 2024.06.28_12.06.37
• 2024.06.27_11.23.46
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• 2024.06.25_11.43.52
• 2024.06.24_08.41.58