SPI_DEVICE/2P Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.514m	217.273ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.330s	24.352us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	824.784us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.760s	2.445ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.300s	777.460us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.590s	838.880us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	824.784us	20	20	100.00
		spi_device_csr_aliasing	16.300s	777.460us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	39.399us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	72.627us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	82.485us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	390.921us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	39.015us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.210s	332.646us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.210s	332.646us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	18.440s	10.203ms	50	50	100.00
		spi_device_tpm_sts_read	1.100s	496.341us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	53.850s	9.410ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.310s	20.247ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.820s	114.589ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.820s	114.589ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.170s	2.835ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.170s	2.835ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.170s	2.835ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.170s	2.835ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.170s	2.835ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	22.750s	6.931ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.148m	38.769ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.148m	38.769ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.148m	38.769ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.416m	4.935ms	50	50	100.00
		spi_device_read_buffer_direct	20.960s	7.666ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.148m	38.769ms	50	50	100.00
		spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.260m	80.130ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.180s	2.725ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.180s	2.725ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.514m	217.273ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.345m	58.513ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.100m	610.687ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	15.626us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	16.326us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.260s	258.532us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.260s	258.532us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.330s	24.352us	5	5	100.00
		spi_device_csr_rw	2.790s	824.784us	20	20	100.00
		spi_device_csr_aliasing	16.300s	777.460us	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	854.047us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.330s	24.352us	5	5	100.00
		spi_device_csr_rw	2.790s	824.784us	20	20	100.00
		spi_device_csr_aliasing	16.300s	777.460us	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	854.047us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.820s	3.464ms	5	5	100.00
		spi_device_tl_intg_err	21.000s	987.360us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.000s	987.360us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.753m	69.301ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Past Results

• Latest
• 2024.07.01_11.10.59
• 2024.06.30_11.26.58
• 2024.06.29_09.49.49
• 2024.06.28_12.06.37
• 2024.06.27_11.23.46
• 2024.06.26_11.21.06
• 2024.06.25_11.43.52