SPI_DEVICE/2P Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.782m	162.307ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	314.987us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.690s	330.641us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.150s	2.362ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.930s	1.932ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.060s	326.726us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.690s	330.641us	20	20	100.00
		spi_device_csr_aliasing	22.930s	1.932ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	36.649us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.040s	100.295us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.920s	22.441us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	55.956us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	17.996us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.970s	721.001us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.970s	721.001us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.010s	9.369ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	179.330us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.650s	20.427ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.830s	7.409ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.570s	143.320ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.570s	143.320ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.050s	14.452ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.050s	14.452ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.050s	14.452ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.050s	14.452ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.050s	14.452ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.940s	11.595ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.358m	9.222ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.358m	9.222ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.358m	9.222ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.310m	22.081ms	50	50	100.00
		spi_device_read_buffer_direct	19.930s	1.911ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.358m	9.222ms	50	50	100.00
		spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.108m	56.760ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	30.850s	5.995ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	30.850s	5.995ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.782m	162.307ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.108m	152.924ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.996m	289.049ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.770s	16.749us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	14.501us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.760s	75.813us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.760s	75.813us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	314.987us	5	5	100.00
		spi_device_csr_rw	2.690s	330.641us	20	20	100.00
		spi_device_csr_aliasing	22.930s	1.932ms	5	5	100.00
		spi_device_same_csr_outstanding	4.150s	761.641us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	314.987us	5	5	100.00
		spi_device_csr_rw	2.690s	330.641us	20	20	100.00
		spi_device_csr_aliasing	22.930s	1.932ms	5	5	100.00
		spi_device_same_csr_outstanding	4.150s	761.641us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.250s	87.366us	5	5	100.00
		spi_device_tl_intg_err	21.320s	3.864ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.320s	3.864ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.348m	83.007ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.02_04.28.46
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• 2024.06.30_11.26.58
• 2024.06.29_09.49.49
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