SPI_DEVICE/2P Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.582m	63.149ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.370s	21.850us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.630s	104.788us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.370s	2.704ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.350s	2.317ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.180s	113.207us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.630s	104.788us	20	20	100.00
		spi_device_csr_aliasing	24.350s	2.317ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	28.999us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.290s	287.533us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	58.920us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	25.638us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	15.485us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.700s	1.138ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.700s	1.138ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.630s	9.365ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	139.866us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.060s	23.107ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.160s	30.013ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.960s	11.949ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.960s	11.949ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.440s	16.886ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.440s	16.886ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.440s	16.886ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.440s	16.886ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.440s	16.886ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.670s	176.894ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.669m	10.406ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.669m	10.406ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.669m	10.406ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.039m	4.564ms	50	50	100.00
		spi_device_read_buffer_direct	23.440s	1.678ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.669m	10.406ms	50	50	100.00
		spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.474m	363.968ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.900s	15.797ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.900s	15.797ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.582m	63.149ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.221m	288.479ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.280m	293.919ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	14.836us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	17.414us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.010s	179.194us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.010s	179.194us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.370s	21.850us	5	5	100.00
		spi_device_csr_rw	2.630s	104.788us	20	20	100.00
		spi_device_csr_aliasing	24.350s	2.317ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	401.801us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.370s	21.850us	5	5	100.00
		spi_device_csr_rw	2.630s	104.788us	20	20	100.00
		spi_device_csr_aliasing	24.350s	2.317ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	401.801us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.320s	238.256us	5	5	100.00
		spi_device_tl_intg_err	23.620s	1.088ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.620s	1.088ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.665m	132.478ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 40.spi_device_flash_mode_ignore_cmds.107037243616692185351242698069613988780572200371954699777163665732156609961236
      Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 753338449 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        UVM_INFO @ 859810606 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/12
        UVM_INFO @ 859810606 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/12
        tl_ul_fuzzy_flash_status_q[i] = 0x13c408
        UVM_INFO @ 1280743918 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/12
      

Past Results

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