SPI_DEVICE/2P Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.947m	274.779ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.370s	23.050us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.960s	975.147us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.260s	1.810ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.080s	2.076ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.340s	236.204us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.960s	975.147us	20	20	100.00
		spi_device_csr_aliasing	23.080s	2.076ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.740s	16.011us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.380s	117.371us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	34.650us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	40.089us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	20.500us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.870s	3.045ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.870s	3.045ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.290s	15.878ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	143.181us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.850s	33.138ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.210s	35.244ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.320s	14.032ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.320s	14.032ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.290s	19.795ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.290s	19.795ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.290s	19.795ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.290s	19.795ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.290s	19.795ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	46.530s	28.118ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.287m	55.571ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.287m	55.571ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.287m	55.571ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.012m	13.590ms	50	50	100.00
		spi_device_read_buffer_direct	17.670s	1.690ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.287m	55.571ms	50	50	100.00
		spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.263m	88.143ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	53.250s	8.866ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	53.250s	8.866ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.947m	274.779ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.283m	77.202ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.953m	246.160ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	13.434us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	21.099us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.790s	779.288us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.790s	779.288us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.370s	23.050us	5	5	100.00
		spi_device_csr_rw	2.960s	975.147us	20	20	100.00
		spi_device_csr_aliasing	23.080s	2.076ms	5	5	100.00
		spi_device_same_csr_outstanding	4.460s	464.573us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.370s	23.050us	5	5	100.00
		spi_device_csr_rw	2.960s	975.147us	20	20	100.00
		spi_device_csr_aliasing	23.080s	2.076ms	5	5	100.00
		spi_device_same_csr_outstanding	4.460s	464.573us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.200s	276.311us	5	5	100.00
		spi_device_tl_intg_err	20.540s	11.257ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.540s	11.257ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.213m	116.034ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.45	94.10	98.62	89.36	97.29	95.43	99.26

Past Results

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