SPI_DEVICE/2P Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.300m	353.950ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.530s	177.607us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.670s	181.023us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.910s	546.871us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.120s	3.782ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.260s	106.013us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.670s	181.023us	20	20	100.00
		spi_device_csr_aliasing	22.120s	3.782ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.730s	11.725us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	289.739us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	27.474us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	25.428us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	18.423us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.540s	2.464ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.540s	2.464ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.880s	10.172ms	50	50	100.00
		spi_device_tpm_sts_read	1.190s	145.262us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.200s	35.716ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.060s	159.378ms	50	50	100.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	45.910s	73.674ms	50	50	100.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	45.910s	73.674ms	50	50	100.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.140s	5.918ms	49	50	98.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.140s	5.918ms	49	50	98.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.140s	5.918ms	49	50	98.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.140s	5.918ms	49	50	98.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.140s	5.918ms	49	50	98.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	26.090s	14.196ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.609m	39.459ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.609m	39.459ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.609m	39.459ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.923m	14.755ms	50	50	100.00
		spi_device_read_buffer_direct	17.630s	5.709ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.609m	39.459ms	50	50	100.00
		spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.638m	38.604ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.200s	14.306ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.200s	14.306ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.300m	353.950ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.127m	471.622ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.097m	141.481ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.840s	14.056us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	42.465us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.220s	194.630us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.220s	194.630us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.530s	177.607us	5	5	100.00
		spi_device_csr_rw	2.670s	181.023us	20	20	100.00
		spi_device_csr_aliasing	22.120s	3.782ms	5	5	100.00
		spi_device_same_csr_outstanding	4.520s	2.611ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.530s	177.607us	5	5	100.00
		spi_device_csr_rw	2.670s	181.023us	20	20	100.00
		spi_device_csr_aliasing	22.120s	3.782ms	5	5	100.00
		spi_device_same_csr_outstanding	4.520s	2.611ms	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.250s	322.531us	5	5	100.00
		spi_device_tl_intg_err	24.740s	1.047ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.740s	1.047ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.995m	372.368ms	50	50	100.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• UVM_ERROR (spi_device_scoreboard.sv:1741) scoreboard [scoreboard] STATUS#* other bits mismatch: {pred (*), pred_fuzzy_q ('{}), act (*)} has 1 failures:
  • Test spi_device_intercept has 1 failures.

    • 35.spi_device_intercept.32158765687785898285014184130250040103610335995593341362809456259454598993967
      Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_intercept/latest/run.log

        UVM_ERROR @ 505767060 ps: (spi_device_scoreboard.sv:1741) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] STATUS#2 other bits mismatch: {pred (0xc6), pred_fuzzy_q ('{}), act (0x89)}
        UVM_ERROR @ 505928676 ps: (spi_device_scoreboard.sv:1741) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] STATUS#2 other bits mismatch: {pred (0xc6), pred_fuzzy_q ('{}), act (0x89)}
        UVM_ERROR @ 506090292 ps: (spi_device_scoreboard.sv:1741) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] STATUS#2 other bits mismatch: {pred (0xc6), pred_fuzzy_q ('{}), act (0x89)}
        UVM_INFO @ 506221606 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 10, test op = 0x3b
        UVM_INFO @ 509221603 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 11, test op = 0x15
      

Past Results

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• 2024.07.03_02.03.44
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