SPI_DEVICE/2P Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.693m	223.520ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	47.211us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.700s	108.755us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.780s	3.769ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.810s	3.643ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.020s	163.410us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.700s	108.755us	20	20	100.00
		spi_device_csr_aliasing	23.810s	3.643ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	14.226us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.410s	63.286us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	31.849us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	65.784us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	39.510us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.310s	285.137us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.310s	285.137us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.560s	33.098ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	207.885us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.050m	81.782ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.790s	29.976ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.240s	17.817ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.240s	17.817ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	29.330s	3.309ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	29.330s	3.309ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	29.330s	3.309ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	29.330s	3.309ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	29.330s	3.309ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	47.920s	73.573ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.114m	103.870ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.114m	103.870ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.114m	103.870ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.006m	17.617ms	50	50	100.00
		spi_device_read_buffer_direct	20.540s	2.061ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.114m	103.870ms	50	50	100.00
		spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	9.128m	111.309ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.670s	28.673ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	20.670s	28.673ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.693m	223.520ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.236m	74.658ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.322m	247.236ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	75.772us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	16.265us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.740s	553.783us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.740s	553.783us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	47.211us	5	5	100.00
		spi_device_csr_rw	2.700s	108.755us	20	20	100.00
		spi_device_csr_aliasing	23.810s	3.643ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	170.184us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	47.211us	5	5	100.00
		spi_device_csr_rw	2.700s	108.755us	20	20	100.00
		spi_device_csr_aliasing	23.810s	3.643ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	170.184us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.240s	562.643us	5	5	100.00
		spi_device_tl_intg_err	23.180s	822.755us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.180s	822.755us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.622m	364.808ms	49	50	98.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.10	98.62	89.36	97.28	95.43	99.26

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

31.spi_device_flash_mode_ignore_cmds.91217452055540356668105665922778185947863134159853131288575642597723886458283
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 24251961466 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 38157150785 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/4
  UVM_INFO @ 38157150785 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/4
  tl_ul_fuzzy_flash_status_q[i] = 0xb37f8
  UVM_INFO @ 56707427771 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/4

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_all has 1 failures.
  - 42.spi_device_flash_all.10481089700288878110840613630050882247052810093657913435356797047973150430401
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest/run.log
```
  Job ID: smart:2dbc5a92-5c2e-4e33-a4ef-3fce82654d4a
```