SPI_DEVICE/2P Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.462m	190.361ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.390s	55.465us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.780s	299.683us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.780s	2.087ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.870s	999.208us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.920s	309.544us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.780s	299.683us	20	20	100.00
		spi_device_csr_aliasing	22.870s	999.208us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	11.554us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.160s	66.655us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	74.367us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	104.185us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	45.879us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.670s	537.876us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.670s	537.876us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.510s	16.491ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	1.225ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.110s	45.094ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.340s	46.497ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.660s	82.929ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.660s	82.929ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.180s	8.245ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.180s	8.245ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.180s	8.245ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.180s	8.245ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.180s	8.245ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.040s	48.867ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.437m	16.337ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.437m	16.337ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.437m	16.337ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	54.270s	7.459ms	50	50	100.00
		spi_device_read_buffer_direct	19.690s	1.684ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.437m	16.337ms	50	50	100.00
		spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.390m	327.669ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.730s	1.578ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.730s	1.578ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.462m	190.361ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.769m	57.729ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.252m	342.002ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	23.011us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	19.248us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.650s	345.393us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.650s	345.393us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.390s	55.465us	5	5	100.00
		spi_device_csr_rw	2.780s	299.683us	20	20	100.00
		spi_device_csr_aliasing	22.870s	999.208us	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	404.957us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.390s	55.465us	5	5	100.00
		spi_device_csr_rw	2.780s	299.683us	20	20	100.00
		spi_device_csr_aliasing	22.870s	999.208us	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	404.957us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.250s	109.170us	5	5	100.00
		spi_device_tl_intg_err	23.770s	7.695ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.770s	7.695ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.253m	80.461ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 24.spi_device_flash_mode_ignore_cmds.67729334308482710876098316641479010520543828385170979738581874207224226164711
      Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job ID: smart:fc2c9b1e-f407-4b87-8ce2-43a74f9ecff4
      

Past Results

• Latest
• 2024.07.06_10.56.45
• 2024.07.05_11.20.15
• 2024.07.04_11.30.04
• 2024.07.03_02.03.44
• 2024.07.02_10.59.15
• 2024.07.02_04.28.46
• 2024.07.01_11.10.59