SPI_DEVICE/2P Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.142m	325.738ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.350s	70.902us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	360.414us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.700s	4.873ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.660s	1.821ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.930s	70.212us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	360.414us	20	20	100.00
		spi_device_csr_aliasing	23.660s	1.821ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	52.092us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.400s	233.216us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.930s	59.961us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.170s	120.891us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	15.840us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.350s	112.819us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.350s	112.819us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.050s	19.718ms	50	50	100.00
		spi_device_tpm_sts_read	1.010s	449.582us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.490s	10.221ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.160s	41.641ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.500s	11.551ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.500s	11.551ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	46.010s	5.265ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	46.010s	5.265ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	46.010s	5.265ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	46.010s	5.265ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	46.010s	5.265ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	32.700s	9.084ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.728m	8.451ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.728m	8.451ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.728m	8.451ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.157m	79.104ms	50	50	100.00
		spi_device_read_buffer_direct	22.420s	7.120ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.728m	8.451ms	50	50	100.00
		spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.094m	311.229ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.600s	6.520ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.600s	6.520ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.142m	325.738ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.891m	642.379ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.193m	381.702ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	66.191us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	26.985us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.410s	1.057ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.410s	1.057ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.350s	70.902us	5	5	100.00
		spi_device_csr_rw	2.860s	360.414us	20	20	100.00
		spi_device_csr_aliasing	23.660s	1.821ms	5	5	100.00
		spi_device_same_csr_outstanding	4.620s	632.868us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.350s	70.902us	5	5	100.00
		spi_device_csr_rw	2.860s	360.414us	20	20	100.00
		spi_device_csr_aliasing	23.660s	1.821ms	5	5	100.00
		spi_device_same_csr_outstanding	4.620s	632.868us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.250s	169.348us	5	5	100.00
		spi_device_tl_intg_err	22.020s	5.250ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.020s	5.250ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.670m	248.560ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.07_10.46.40
• 2024.07.06_10.56.45
• 2024.07.05_11.20.15
• 2024.07.04_11.30.04
• 2024.07.03_02.03.44
• 2024.07.02_10.59.15
• 2024.07.02_04.28.46