SPI_DEVICE/2P Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.107m	74.549ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	68.843us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.100s	984.143us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.370s	7.075ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.490s	3.133ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.030s	53.065us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.100s	984.143us	20	20	100.00
		spi_device_csr_aliasing	16.490s	3.133ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.064us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.210s	88.910us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.830s	38.118us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	366.095us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	23.965us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.890s	267.325us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.890s	267.325us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.110s	8.512ms	50	50	100.00
		spi_device_tpm_sts_read	1.010s	107.370us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.540s	19.047ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	23.480s	15.932ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	22.320s	22.793ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	22.320s	22.793ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	46.510s	5.521ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	46.510s	5.521ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	46.510s	5.521ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	46.510s	5.521ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	46.510s	5.521ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	40.460s	43.664ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.306m	78.254ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.306m	78.254ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.306m	78.254ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.390s	5.219ms	50	50	100.00
		spi_device_read_buffer_direct	23.180s	3.850ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.306m	78.254ms	50	50	100.00
		spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.990m	35.362ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.230s	5.796ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.230s	5.796ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.107m	74.549ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.380m	317.797ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.188m	128.377ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	17.435us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	53.046us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.550s	944.386us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.550s	944.386us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	68.843us	5	5	100.00
		spi_device_csr_rw	3.100s	984.143us	20	20	100.00
		spi_device_csr_aliasing	16.490s	3.133ms	5	5	100.00
		spi_device_same_csr_outstanding	4.780s	417.666us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	68.843us	5	5	100.00
		spi_device_csr_rw	3.100s	984.143us	20	20	100.00
		spi_device_csr_aliasing	16.490s	3.133ms	5	5	100.00
		spi_device_same_csr_outstanding	4.780s	417.666us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.250s	86.478us	5	5	100.00
		spi_device_tl_intg_err	24.100s	1.249ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.100s	1.249ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.871m	57.180ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.10	98.62	89.36	97.28	95.43	99.26

Past Results

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• 2024.07.08_10.26.31
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