SPI_DEVICE/2P Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.255m	255.061ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	44.622us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.600s	387.085us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.590s	2.742ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.260s	315.801us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.190s	422.097us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.600s	387.085us	20	20	100.00
		spi_device_csr_aliasing	20.260s	315.801us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	13.181us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.300s	310.118us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	70.842us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	57.620us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	39.176us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.860s	254.191us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.860s	254.191us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.290s	59.110ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	151.477us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.040s	30.557ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.510s	13.111ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.400s	51.343ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.400s	51.343ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.390s	18.294ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.390s	18.294ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.390s	18.294ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.390s	18.294ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.390s	18.294ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.720s	54.207ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.421m	59.655ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.421m	59.655ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.421m	59.655ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	59.170s	9.986ms	50	50	100.00
		spi_device_read_buffer_direct	21.350s	1.536ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.421m	59.655ms	50	50	100.00
		spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.007m	327.594ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.340s	10.109ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.340s	10.109ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.255m	255.061ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.761m	70.396ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.676m	127.878ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	14.622us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.870s	44.969us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.350s	173.935us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.350s	173.935us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	44.622us	5	5	100.00
		spi_device_csr_rw	2.600s	387.085us	20	20	100.00
		spi_device_csr_aliasing	20.260s	315.801us	5	5	100.00
		spi_device_same_csr_outstanding	4.150s	1.000ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	44.622us	5	5	100.00
		spi_device_csr_rw	2.600s	387.085us	20	20	100.00
		spi_device_csr_aliasing	20.260s	315.801us	5	5	100.00
		spi_device_same_csr_outstanding	4.150s	1.000ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.190s	99.931us	5	5	100.00
		spi_device_tl_intg_err	24.460s	1.074ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.460s	1.074ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	31.249m	1.500s	48	50	96.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

15.spi_device_flash_mode_ignore_cmds.61810048064885279620760350712016917184820921220977539617539322221178895435315
Line 295, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 35923374967 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0x8aaee8
  tl_ul_fuzzy_flash_status_q[i] = 0xf5427c
  UVM_INFO @ 37801605967 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 10/11
  UVM_INFO @ 37839494967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 35.spi_device_flash_mode_ignore_cmds.76579579797867505776098322965680122151329281216246572191016655998057076598747
    Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```