SPI_DEVICE/2P Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.126m	76.846ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	186.163us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.510s	90.750us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.880s	2.178ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.400s	1.284ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.030s	55.850us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.510s	90.750us	20	20	100.00
		spi_device_csr_aliasing	23.400s	1.284ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.730s	35.344us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.280s	222.380us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.910s	17.969us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	33.425us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	15.251us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.010s	1.107ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.010s	1.107ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.190s	30.240ms	50	50	100.00
		spi_device_tpm_sts_read	0.970s	126.104us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.160s	8.910ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	18.670s	5.022ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.910s	49.164ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.910s	49.164ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.190s	6.156ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.190s	6.156ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.190s	6.156ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.190s	6.156ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.190s	6.156ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	24.150s	165.589ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.795m	52.242ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.795m	52.242ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.795m	52.242ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	44.420s	3.732ms	50	50	100.00
		spi_device_read_buffer_direct	19.750s	8.121ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.795m	52.242ms	50	50	100.00
		spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.214m	292.642ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.970s	9.184ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.970s	9.184ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.126m	76.846ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.656m	156.764ms	50	50	100.00
V2	stress_all	spi_device_stress_all	22.661m	263.208ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.750s	12.681us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	17.614us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.010s	1.039ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.010s	1.039ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	186.163us	5	5	100.00
		spi_device_csr_rw	2.510s	90.750us	20	20	100.00
		spi_device_csr_aliasing	23.400s	1.284ms	5	5	100.00
		spi_device_same_csr_outstanding	4.820s	1.130ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	186.163us	5	5	100.00
		spi_device_csr_rw	2.510s	90.750us	20	20	100.00
		spi_device_csr_aliasing	23.400s	1.284ms	5	5	100.00
		spi_device_same_csr_outstanding	4.820s	1.130ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.150s	383.638us	5	5	100.00
		spi_device_tl_intg_err	25.480s	4.353ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.480s	4.353ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.114m	77.316ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.45	94.08	98.62	89.36	97.29	95.43	99.21

Past Results

• Latest
• 2024.07.11_10.46.44
• 2024.07.10_10.55.29
• 2024.07.08_10.26.31
• 2024.07.07_10.46.40
• 2024.07.06_10.56.45
• 2024.07.05_11.20.15
• 2024.07.04_11.30.04