SPI_DEVICE/2P Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.352m	106.615ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.350s	172.342us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.060s	273.055us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.920s	22.493ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.550s	2.086ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.240s	2.336ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.060s	273.055us	20	20	100.00
		spi_device_csr_aliasing	20.550s	2.086ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	14.201us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.000s	28.378us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	21.093us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	17.350us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	19.716us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.540s	139.279us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.540s	139.279us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.960s	9.806ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	139.292us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	57.920s	10.392ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	44.630s	17.096ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.250s	41.261ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.250s	41.261ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	45.220s	13.672ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	45.220s	13.672ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	45.220s	13.672ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	45.220s	13.672ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	45.220s	13.672ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.390s	11.262ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.032m	13.726ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.032m	13.726ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.032m	13.726ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.488m	10.159ms	50	50	100.00
		spi_device_read_buffer_direct	21.430s	29.974ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.032m	13.726ms	50	50	100.00
		spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.554m	62.766ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.190s	1.806ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.190s	1.806ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.352m	106.615ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.723m	80.422ms	50	50	100.00
V2	stress_all	spi_device_stress_all	23.495m	591.910ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	13.245us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	14.283us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.240s	1.188ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.240s	1.188ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.350s	172.342us	5	5	100.00
		spi_device_csr_rw	3.060s	273.055us	20	20	100.00
		spi_device_csr_aliasing	20.550s	2.086ms	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	1.589ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.350s	172.342us	5	5	100.00
		spi_device_csr_rw	3.060s	273.055us	20	20	100.00
		spi_device_csr_aliasing	20.550s	2.086ms	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	1.589ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.220s	360.397us	5	5	100.00
		spi_device_tl_intg_err	20.540s	3.371ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.540s	3.371ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.296m	208.781ms	48	50	96.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 38.spi_device_flash_mode_ignore_cmds.65754543726844686784107355581449602440297836125358882818108699127015218338327
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:c076be61-6e5e-4393-87ca-0aa54ffe152d
```

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

40.spi_device_flash_mode_ignore_cmds.20442333305540519015223630243033777620390577365222554385307607802165489174260
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 1014289525 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 1761994125 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/14
  UVM_INFO @ 1761994125 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/14
  tl_ul_fuzzy_flash_status_q[i] = 0x3a1e28
  tl_ul_fuzzy_flash_status_q[i] = 0xf46ea4