SPI_DEVICE/2P Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.605m	105.609ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	94.551us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.890s	501.565us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.690s	11.267ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.970s	1.074ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.950s	163.366us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.890s	501.565us	20	20	100.00
		spi_device_csr_aliasing	22.970s	1.074ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.730s	20.857us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.030s	158.512us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	58.704us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	27.561us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	60.446us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.250s	249.443us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.250s	249.443us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	18.490s	7.219ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	444.018us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.250s	18.066ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	42.060s	81.367ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.600s	21.362ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.600s	21.362ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	42.600s	3.503ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	42.600s	3.503ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	42.600s	3.503ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	42.600s	3.503ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	42.600s	3.503ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.140s	28.098ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.486m	13.119ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.486m	13.119ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.486m	13.119ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.872m	6.258ms	50	50	100.00
		spi_device_read_buffer_direct	14.790s	1.042ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.486m	13.119ms	50	50	100.00
		spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.749m	48.502ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.120s	3.497ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.120s	3.497ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.605m	105.609ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.917m	266.105ms	50	50	100.00
V2	stress_all	spi_device_stress_all	23.844m	2.108s	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	16.266us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	90.354us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.220s	213.548us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.220s	213.548us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	94.551us	5	5	100.00
		spi_device_csr_rw	2.890s	501.565us	20	20	100.00
		spi_device_csr_aliasing	22.970s	1.074ms	5	5	100.00
		spi_device_same_csr_outstanding	4.940s	217.480us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	94.551us	5	5	100.00
		spi_device_csr_rw	2.890s	501.565us	20	20	100.00
		spi_device_csr_aliasing	22.970s	1.074ms	5	5	100.00
		spi_device_same_csr_outstanding	4.940s	217.480us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.210s	270.377us	5	5	100.00
		spi_device_tl_intg_err	24.240s	3.180ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.240s	3.180ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.855m	77.046ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Past Results

• Latest
• 2024.07.13_08.34.35
• 2024.07.12_09.23.11
• 2024.07.11_10.46.44
• 2024.07.10_10.55.29
• 2024.07.08_10.26.31
• 2024.07.07_10.46.40
• 2024.07.06_10.56.45