SPI_DEVICE/2P Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.883m	89.931ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.170s	37.081us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.960s	98.842us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.520s	5.508ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.030s	2.855ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.500s	177.530us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.960s	98.842us	20	20	100.00
		spi_device_csr_aliasing	25.030s	2.855ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	10.291us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.350s	79.174us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	13.668us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	28.211us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	44.194us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.160s	262.537us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.160s	262.537us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	18.390s	10.601ms	50	50	100.00
		spi_device_tpm_sts_read	1.030s	92.186us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.180s	9.225ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	26.570s	8.991ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.150s	14.041ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.150s	14.041ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.580s	12.678ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.580s	12.678ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.580s	12.678ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.580s	12.678ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.580s	12.678ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.750s	9.602ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.090m	14.469ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.090m	14.469ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.090m	14.469ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.735m	8.014ms	50	50	100.00
		spi_device_read_buffer_direct	21.510s	9.099ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.090m	14.469ms	50	50	100.00
		spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.512m	240.460ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.510s	7.461ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.510s	7.461ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.883m	89.931ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.120m	777.694ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.859m	1.008s	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	14.807us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	22.952us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.650s	420.089us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.650s	420.089us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.170s	37.081us	5	5	100.00
		spi_device_csr_rw	2.960s	98.842us	20	20	100.00
		spi_device_csr_aliasing	25.030s	2.855ms	5	5	100.00
		spi_device_same_csr_outstanding	4.670s	313.825us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.170s	37.081us	5	5	100.00
		spi_device_csr_rw	2.960s	98.842us	20	20	100.00
		spi_device_csr_aliasing	25.030s	2.855ms	5	5	100.00
		spi_device_same_csr_outstanding	4.670s	313.825us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.240s	439.096us	5	5	100.00
		spi_device_tl_intg_err	22.610s	865.150us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.610s	865.150us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.178m	107.854ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.10	98.62	89.36	97.29	95.43	99.26

Past Results

• Latest
• 2024.07.14_08.56.45
• 2024.07.13_08.34.35
• 2024.07.12_09.23.11
• 2024.07.11_10.46.44
• 2024.07.10_10.55.29
• 2024.07.08_10.26.31
• 2024.07.07_10.46.40