SPI_DEVICE/2P Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.885m	369.962ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	159.649us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.950s	206.362us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.940s	11.233ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.700s	2.517ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.070s	60.444us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.950s	206.362us	20	20	100.00
		spi_device_csr_aliasing	24.700s	2.517ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	12.942us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.320s	74.871us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	19.673us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	17.597us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	54.936us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.060s	1.566ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.060s	1.566ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.390s	89.942ms	50	50	100.00
		spi_device_tpm_sts_read	1.100s	187.174us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.020s	39.842ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.800s	10.990ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.580s	45.410ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.580s	45.410ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.440s	11.830ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.440s	11.830ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.440s	11.830ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.440s	11.830ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.440s	11.830ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.890s	21.946ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.287m	24.026ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.287m	24.026ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.287m	24.026ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	42.800s	2.768ms	50	50	100.00
		spi_device_read_buffer_direct	19.090s	1.430ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.287m	24.026ms	50	50	100.00
		spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.019m	228.161ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.610s	17.418ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.610s	17.418ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.885m	369.962ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.383m	150.424ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.470m	147.516ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	23.042us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	52.766us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.160s	543.121us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.160s	543.121us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	159.649us	5	5	100.00
		spi_device_csr_rw	2.950s	206.362us	20	20	100.00
		spi_device_csr_aliasing	24.700s	2.517ms	5	5	100.00
		spi_device_same_csr_outstanding	4.330s	1.044ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	159.649us	5	5	100.00
		spi_device_csr_rw	2.950s	206.362us	20	20	100.00
		spi_device_csr_aliasing	24.700s	2.517ms	5	5	100.00
		spi_device_same_csr_outstanding	4.330s	1.044ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.220s	182.620us	5	5	100.00
		spi_device_tl_intg_err	23.110s	2.432ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.110s	2.432ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.206m	78.322ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.29	95.43	99.26

Past Results

• Latest
• 2024.07.15_09.41.02
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• 2024.07.13_08.34.35
• 2024.07.12_09.23.11
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