SPI_DEVICE/2P Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.578m	57.747ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	83.437us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.920s	253.261us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.900s	12.352ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.330s	1.414ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.830s	266.933us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.920s	253.261us	20	20	100.00
		spi_device_csr_aliasing	15.330s	1.414ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	36.418us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.280s	112.939us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	41.977us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.170s	34.702us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	27.857us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.800s	478.487us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.800s	478.487us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.480s	7.424ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	122.393us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.440s	7.958ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.280s	41.712ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.450s	20.882ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.450s	20.882ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.670s	9.018ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.670s	9.018ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.670s	9.018ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.670s	9.018ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.670s	9.018ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.390s	37.582ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.858m	29.969ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.858m	29.969ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.858m	29.969ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.407m	6.652ms	50	50	100.00
		spi_device_read_buffer_direct	18.780s	6.604ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.858m	29.969ms	50	50	100.00
		spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.730m	81.617ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.880s	4.030ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.880s	4.030ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.578m	57.747ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.933m	231.405ms	50	50	100.00
V2	stress_all	spi_device_stress_all	9.278m	61.061ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	39.765us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	14.077us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.790s	70.152us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.790s	70.152us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	83.437us	5	5	100.00
		spi_device_csr_rw	2.920s	253.261us	20	20	100.00
		spi_device_csr_aliasing	15.330s	1.414ms	5	5	100.00
		spi_device_same_csr_outstanding	4.900s	923.694us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	83.437us	5	5	100.00
		spi_device_csr_rw	2.920s	253.261us	20	20	100.00
		spi_device_csr_aliasing	15.330s	1.414ms	5	5	100.00
		spi_device_same_csr_outstanding	4.900s	923.694us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.230s	344.691us	5	5	100.00
		spi_device_tl_intg_err	21.510s	3.315ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.510s	3.315ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.733m	675.682ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.45	94.08	98.62	89.36	97.31	95.43	99.21

Failure Buckets

• UVM_ERROR (spi_device_scoreboard.sv:2798) [scoreboard] Check failed upload_cmd_q.size == * (* [*] vs * [*]) has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 49.spi_device_flash_mode_ignore_cmds.36840479070480638801443879527982284218514771191943055842863237848889572568380
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 31311577360 ps: (spi_device_scoreboard.sv:2798) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size == 0 (1 [0x1] vs 0 [0x0])
        UVM_ERROR @ 31311577360 ps: (spi_device_scoreboard.sv:2799) [uvm_test_top.env.scoreboard] Check failed upload_addr_q.size == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 31311577360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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