SPI_DEVICE/2P Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.746m	72.356ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	192.098us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.650s	117.470us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.060s	9.347ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.520s	326.547us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.750s	641.047us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.650s	117.470us	20	20	100.00
		spi_device_csr_aliasing	22.520s	326.547us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	18.381us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.290s	98.359us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	123.968us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	63.780us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	18.209us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.540s	230.058us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.540s	230.058us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.070s	7.833ms	50	50	100.00
		spi_device_tpm_sts_read	1.130s	395.252us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.420s	41.829ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	20.330s	13.023ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.940s	28.344ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.940s	28.344ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.060s	8.291ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.060s	8.291ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.060s	8.291ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.060s	8.291ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.060s	8.291ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.110s	9.858ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.914m	12.178ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.914m	12.178ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.914m	12.178ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	38.260s	4.823ms	50	50	100.00
		spi_device_read_buffer_direct	19.510s	18.926ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.914m	12.178ms	50	50	100.00
		spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.565m	160.909ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.830s	12.429ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	20.830s	12.429ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.746m	72.356ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.387m	83.512ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.779m	125.517ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	13.319us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	13.414us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.140s	201.090us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.140s	201.090us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	192.098us	5	5	100.00
		spi_device_csr_rw	2.650s	117.470us	20	20	100.00
		spi_device_csr_aliasing	22.520s	326.547us	5	5	100.00
		spi_device_same_csr_outstanding	4.380s	193.302us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	192.098us	5	5	100.00
		spi_device_csr_rw	2.650s	117.470us	20	20	100.00
		spi_device_csr_aliasing	22.520s	326.547us	5	5	100.00
		spi_device_same_csr_outstanding	4.380s	193.302us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.300s	89.876us	5	5	100.00
		spi_device_tl_intg_err	24.410s	20.565ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.410s	20.565ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	19.168m	1.500s	49	50	98.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:2235) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

3.spi_device_cfg_cmd.562140977600152030893271783417992310767033391029903956908160086492778809297
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 533554323 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9c8f66) != exp '{'{other_status:'h195137, wel:'h1, busy:'h0}, '{other_status:'h37bb6f, wel:'h1, busy:'h0}, '{other_status:'h2723d9, wel:'h0, busy:'h0}, '{other_status:'h37bb6f, wel:'h0, busy:'h0}, '{other_status:'h2723d9, wel:'h0, busy:'h0}}
  UVM_INFO @ 533727791 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 8, test op = 0x4
  UVM_ERROR @ 534023707 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9c8f66) != exp '{'{other_status:'h195137, wel:'h1, busy:'h0}, '{other_status:'h37bb6f, wel:'h1, busy:'h0}, '{other_status:'h2723d9, wel:'h0, busy:'h0}, '{other_status:'h37bb6f, wel:'h0, busy:'h0}, '{other_status:'h2723d9, wel:'h0, busy:'h0}}
  UVM_INFO @ 535431859 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 9, test op = 0x4
  UVM_INFO @ 537023683 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 10, test op = 0x6

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 23.spi_device_flash_mode_ignore_cmds.31028277620143444920978104333227262901837919277299044254823643876002332742601
    Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```