SPI_DEVICE/2P Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.874m	337.949ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.020s	33.254us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.760s	514.886us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.500s	5.578ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.960s	4.490ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.960s	518.648us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.760s	514.886us	20	20	100.00
		spi_device_csr_aliasing	22.960s	4.490ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.917us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.270s	63.109us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	30.536us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.200s	34.034us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	18.849us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.220s	615.513us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.220s	615.513us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.460s	36.386ms	50	50	100.00
		spi_device_tpm_sts_read	1.210s	158.090us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.160s	8.231ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	18.560s	27.935ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.190s	54.046ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.190s	54.046ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	47.630s	4.937ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	47.630s	4.937ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	47.630s	4.937ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	47.630s	4.937ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	47.630s	4.937ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	47.520s	170.228ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.963m	49.932ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.963m	49.932ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.963m	49.932ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.131m	8.137ms	50	50	100.00
		spi_device_read_buffer_direct	20.160s	1.894ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.963m	49.932ms	50	50	100.00
		spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.934m	58.016ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	18.370s	6.886ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	18.370s	6.886ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.874m	337.949ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.778m	141.183ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.706m	91.095ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	43.402us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	54.284us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.400s	595.883us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.400s	595.883us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.020s	33.254us	5	5	100.00
		spi_device_csr_rw	2.760s	514.886us	20	20	100.00
		spi_device_csr_aliasing	22.960s	4.490ms	5	5	100.00
		spi_device_same_csr_outstanding	4.600s	1.289ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.020s	33.254us	5	5	100.00
		spi_device_csr_rw	2.760s	514.886us	20	20	100.00
		spi_device_csr_aliasing	22.960s	4.490ms	5	5	100.00
		spi_device_same_csr_outstanding	4.600s	1.289ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.110s	1.105ms	5	5	100.00
		spi_device_tl_intg_err	23.750s	6.059ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.750s	6.059ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.718m	307.887ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.45	94.08	98.62	89.36	97.29	95.43	99.26

Past Results

• Latest
• 2024.07.18_09.33.49
• 2024.07.17_09.46.12
• 2024.07.16_09.53.23
• 2024.07.15_09.41.02
• 2024.07.14_08.56.45
• 2024.07.13_08.34.35
• 2024.07.12_09.23.11