SPI_DEVICE/2P Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.076m	145.119ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	366.985us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.770s	143.351us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.900s	2.173ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.880s	1.146ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.920s	56.261us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.770s	143.351us	20	20	100.00
		spi_device_csr_aliasing	23.880s	1.146ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	21.212us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	49.259us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	76.554us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	358.541us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	25.694us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.190s	1.731ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.190s	1.731ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.700s	39.179ms	50	50	100.00
		spi_device_tpm_sts_read	1.010s	81.642us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	57.340s	10.243ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	39.600s	19.445ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.380s	57.488ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.380s	57.488ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	44.590s	8.177ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	44.590s	8.177ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	44.590s	8.177ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	44.590s	8.177ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	44.590s	8.177ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.140s	14.302ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.685m	10.299ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.685m	10.299ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.685m	10.299ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.509m	34.638ms	50	50	100.00
		spi_device_read_buffer_direct	19.210s	5.539ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.685m	10.299ms	50	50	100.00
		spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.043m	54.309ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.870s	11.454ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.870s	11.454ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.076m	145.119ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.907m	248.983ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.183m	114.653ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	111.745us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	18.712us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.020s	190.648us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.020s	190.648us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	366.985us	5	5	100.00
		spi_device_csr_rw	2.770s	143.351us	20	20	100.00
		spi_device_csr_aliasing	23.880s	1.146ms	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	217.298us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	366.985us	5	5	100.00
		spi_device_csr_rw	2.770s	143.351us	20	20	100.00
		spi_device_csr_aliasing	23.880s	1.146ms	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	217.298us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.240s	86.749us	5	5	100.00
		spi_device_tl_intg_err	22.810s	4.171ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.810s	4.171ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.802m	334.147ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.19_09.02.00
• 2024.07.18_09.33.49
• 2024.07.17_09.46.12
• 2024.07.16_09.53.23
• 2024.07.15_09.41.02
• 2024.07.14_08.56.45
• 2024.07.13_08.34.35