SPI_DEVICE/2P Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.110m	90.536ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.250s	33.483us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.970s	454.851us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.510s	9.741ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.570s	2.286ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.810s	302.984us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.970s	454.851us	20	20	100.00
		spi_device_csr_aliasing	24.570s	2.286ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.770s	10.303us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.820s	97.944us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	23.895us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	65.304us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	16.281us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.580s	867.577us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.580s	867.577us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.420s	8.713ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	93.344us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.970s	19.476ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	19.880s	6.270ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.560s	48.269ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.560s	48.269ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.490s	5.257ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.490s	5.257ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.490s	5.257ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.490s	5.257ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.490s	5.257ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.550s	43.374ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.663m	22.333ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.663m	22.333ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.663m	22.333ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.015m	19.837ms	50	50	100.00
		spi_device_read_buffer_direct	17.280s	25.799ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.663m	22.333ms	50	50	100.00
		spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.174m	70.833ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.670s	5.238ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.670s	5.238ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.110m	90.536ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.716m	364.213ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.726m	207.306ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	13.886us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	229.520us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.240s	86.007us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.240s	86.007us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.250s	33.483us	5	5	100.00
		spi_device_csr_rw	2.970s	454.851us	20	20	100.00
		spi_device_csr_aliasing	24.570s	2.286ms	5	5	100.00
		spi_device_same_csr_outstanding	4.680s	221.771us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.250s	33.483us	5	5	100.00
		spi_device_csr_rw	2.970s	454.851us	20	20	100.00
		spi_device_csr_aliasing	24.570s	2.286ms	5	5	100.00
		spi_device_same_csr_outstanding	4.680s	221.771us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.210s	368.468us	5	5	100.00
		spi_device_tl_intg_err	24.130s	1.735ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.130s	1.735ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.210m	148.995ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.20_10.01.54
• 2024.07.19_09.02.00
• 2024.07.18_09.33.49
• 2024.07.17_09.46.12
• 2024.07.16_09.53.23
• 2024.07.15_09.41.02
• 2024.07.14_08.56.45