SPI_DEVICE/2P Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.683m	280.930ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.530s	189.666us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.090s	175.175us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.060s	3.481ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.800s	8.543ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.040s	307.931us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.090s	175.175us	20	20	100.00
		spi_device_csr_aliasing	21.800s	8.543ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	12.129us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.330s	128.404us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	21.545us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	245.621us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	16.967us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.240s	714.827us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.240s	714.827us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.020s	9.954ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	214.186us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	56.530s	68.082ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.670s	26.673ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.690s	66.454ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.690s	66.454ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.950s	2.598ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.950s	2.598ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.950s	2.598ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.950s	2.598ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.950s	2.598ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.510s	36.830ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.311m	66.026ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.311m	66.026ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.311m	66.026ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	55.460s	19.792ms	50	50	100.00
		spi_device_read_buffer_direct	17.480s	10.658ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.311m	66.026ms	50	50	100.00
		spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.646m	84.784ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	38.220s	17.032ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	38.220s	17.032ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.683m	280.930ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.928m	94.958ms	50	50	100.00
V2	stress_all	spi_device_stress_all	26.620m	673.807ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	16.144us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	33.116us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.760s	2.615ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.760s	2.615ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.530s	189.666us	5	5	100.00
		spi_device_csr_rw	3.090s	175.175us	20	20	100.00
		spi_device_csr_aliasing	21.800s	8.543ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	1.576ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.530s	189.666us	5	5	100.00
		spi_device_csr_rw	3.090s	175.175us	20	20	100.00
		spi_device_csr_aliasing	21.800s	8.543ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	1.576ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.310s	482.354us	5	5	100.00
		spi_device_tl_intg_err	24.630s	8.501ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.630s	8.501ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.649m	55.784ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.21_08.37.39
• 2024.07.20_10.01.54
• 2024.07.19_09.02.00
• 2024.07.18_09.33.49
• 2024.07.17_09.46.12
• 2024.07.16_09.53.23
• 2024.07.15_09.41.02