SPI_DEVICE/2P Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.082m	68.502ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	185.677us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	93.125us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.640s	10.777ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.290s	324.383us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.940s	665.327us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	93.125us	20	20	100.00
		spi_device_csr_aliasing	22.290s	324.383us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	13.260us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.410s	31.292us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	36.729us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	152.130us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	16.964us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.300s	698.060us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.300s	698.060us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.740s	8.071ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	407.061us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.790s	43.008ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	22.120s	5.901ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.060s	49.766ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.060s	49.766ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.160s	13.753ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.160s	13.753ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.160s	13.753ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.160s	13.753ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.160s	13.753ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.180s	41.419ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.305m	29.953ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.305m	29.953ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.305m	29.953ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.241m	16.739ms	50	50	100.00
		spi_device_read_buffer_direct	26.800s	2.035ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.305m	29.953ms	50	50	100.00
		spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.348m	66.714ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.590s	2.509ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.590s	2.509ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.082m	68.502ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.268m	79.383ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.934m	104.666ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	42.990us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	15.240us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.200s	186.240us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.200s	186.240us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	185.677us	5	5	100.00
		spi_device_csr_rw	2.720s	93.125us	20	20	100.00
		spi_device_csr_aliasing	22.290s	324.383us	5	5	100.00
		spi_device_same_csr_outstanding	4.400s	647.296us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	185.677us	5	5	100.00
		spi_device_csr_rw	2.720s	93.125us	20	20	100.00
		spi_device_csr_aliasing	22.290s	324.383us	5	5	100.00
		spi_device_same_csr_outstanding	4.400s	647.296us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.170s	1.549ms	5	5	100.00
		spi_device_tl_intg_err	23.840s	8.853ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.840s	8.853ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.927m	341.450ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 45.spi_device_flash_mode_ignore_cmds.59666417773585860645648593882521937664828558083370785625613372782265180056536
      Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job ID: smart:220a77d7-58fc-467a-924e-a15c95b832c0
      

Past Results

• Latest
• 2024.07.22_08.56.43
• 2024.07.21_08.37.39
• 2024.07.20_10.01.54
• 2024.07.19_09.02.00
• 2024.07.18_09.33.49
• 2024.07.17_09.46.12
• 2024.07.16_09.53.23