SPI_DEVICE/2P Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.955m	402.141ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.220s	66.584us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.540s	37.865us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.320s	547.642us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.110s	10.329ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.340s	64.700us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.540s	37.865us	20	20	100.00
		spi_device_csr_aliasing	24.110s	10.329ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	74.306us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	257.387us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.830s	49.693us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.240s	54.511us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	33.731us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.900s	381.108us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.900s	381.108us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.570s	6.910ms	50	50	100.00
		spi_device_tpm_sts_read	1.030s	156.535us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.670s	62.464ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.000s	43.866ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.540s	121.622ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.540s	121.622ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.870s	6.016ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.870s	6.016ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.870s	6.016ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.870s	6.016ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.870s	6.016ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.720s	9.943ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.357m	15.307ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.357m	15.307ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.357m	15.307ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	52.080s	4.371ms	50	50	100.00
		spi_device_read_buffer_direct	26.640s	1.974ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.357m	15.307ms	50	50	100.00
		spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.720m	67.499ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.650s	15.614ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.650s	15.614ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.955m	402.141ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.621m	180.857ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.989m	219.119ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	11.658us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	53.835us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.770s	83.736us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.770s	83.736us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.220s	66.584us	5	5	100.00
		spi_device_csr_rw	2.540s	37.865us	20	20	100.00
		spi_device_csr_aliasing	24.110s	10.329ms	5	5	100.00
		spi_device_same_csr_outstanding	4.270s	850.628us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.220s	66.584us	5	5	100.00
		spi_device_csr_rw	2.540s	37.865us	20	20	100.00
		spi_device_csr_aliasing	24.110s	10.329ms	5	5	100.00
		spi_device_same_csr_outstanding	4.270s	850.628us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.220s	116.255us	5	5	100.00
		spi_device_tl_intg_err	22.440s	3.563ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.440s	3.563ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.282m	305.197ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.10	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.23_08.57.28
• 2024.07.22_08.56.43
• 2024.07.21_08.37.39
• 2024.07.20_10.01.54
• 2024.07.19_09.02.00
• 2024.07.18_09.33.49
• 2024.07.17_09.46.12