SPI_DEVICE/2P Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.442m	63.137ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	47.140us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.750s	121.577us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.900s	1.840ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.420s	1.564ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.950s	685.734us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.750s	121.577us	20	20	100.00
		spi_device_csr_aliasing	16.420s	1.564ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	34.462us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.140s	52.925us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	22.088us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.080s	35.976us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	14.889us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.380s	1.051ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.380s	1.051ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.650s	20.908ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	190.840us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	39.890s	24.700ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	22.130s	78.933ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	40.580s	31.820ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	40.580s	31.820ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.290s	61.035ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.290s	61.035ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.290s	61.035ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.290s	61.035ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.290s	61.035ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.030s	23.004ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.700m	46.417ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.700m	46.417ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.700m	46.417ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.442m	13.311ms	50	50	100.00
		spi_device_read_buffer_direct	20.930s	3.637ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.700m	46.417ms	50	50	100.00
		spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.547m	40.066ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.570s	1.425ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.570s	1.425ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.442m	63.137ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.030m	120.649ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.748m	130.155ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	23.643us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	18.828us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.990s	385.002us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.990s	385.002us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	47.140us	5	5	100.00
		spi_device_csr_rw	2.750s	121.577us	20	20	100.00
		spi_device_csr_aliasing	16.420s	1.564ms	5	5	100.00
		spi_device_same_csr_outstanding	4.210s	191.385us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	47.140us	5	5	100.00
		spi_device_csr_rw	2.750s	121.577us	20	20	100.00
		spi_device_csr_aliasing	16.420s	1.564ms	5	5	100.00
		spi_device_same_csr_outstanding	4.210s	191.385us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.190s	331.867us	5	5	100.00
		spi_device_tl_intg_err	19.940s	306.047us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.940s	306.047us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.801m	106.551ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Past Results

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