SPI_DEVICE/2P Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.606m	95.039ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	289.178us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.160s	886.514us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.330s	19.355ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.010s	3.726ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.000s	295.506us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.160s	886.514us	20	20	100.00
		spi_device_csr_aliasing	23.010s	3.726ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	49.092us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.760s	87.024us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	23.522us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	35.298us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	30.785us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.070s	908.573us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.070s	908.573us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.000s	37.200ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	234.188us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.790s	8.918ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.310s	29.143ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.280s	79.468ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.280s	79.468ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.470s	2.302ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.470s	2.302ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.470s	2.302ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.470s	2.302ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.470s	2.302ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	32.130s	38.848ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.013m	32.304ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.013m	32.304ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.013m	32.304ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	53.790s	25.002ms	50	50	100.00
		spi_device_read_buffer_direct	18.920s	5.815ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.013m	32.304ms	50	50	100.00
		spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.843m	91.528ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.010s	12.886ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	27.010s	12.886ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.606m	95.039ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.704m	339.086ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.594m	479.872ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	43.726us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	16.743us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.180s	798.406us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.180s	798.406us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	289.178us	5	5	100.00
		spi_device_csr_rw	3.160s	886.514us	20	20	100.00
		spi_device_csr_aliasing	23.010s	3.726ms	5	5	100.00
		spi_device_same_csr_outstanding	4.900s	219.877us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	289.178us	5	5	100.00
		spi_device_csr_rw	3.160s	886.514us	20	20	100.00
		spi_device_csr_aliasing	23.010s	3.726ms	5	5	100.00
		spi_device_same_csr_outstanding	4.900s	219.877us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.180s	183.922us	5	5	100.00
		spi_device_tl_intg_err	21.590s	816.387us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.590s	816.387us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.654m	103.373ms	50	50	100.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:2235) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}}

has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

27.spi_device_cfg_cmd.14713247499648028884298437395220949486734315443534357733168578974077431175425
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 2558530833 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x60cada) != exp '{'{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}, '{other_status:'h3c81f2, wel:'h0, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2559841187 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x60cada) != exp '{'{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}, '{other_status:'h3c81f2, wel:'h0, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2560220500 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x60cada) != exp '{'{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}, '{other_status:'h3c81f2, wel:'h0, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2561151541 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x60cada) != exp '{'{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}, '{other_status:'h3c81f2, wel:'h0, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2561530854 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x60cada) != exp '{'{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h60a5f, wel:'h1, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}, '{other_status:'h3c81f2, wel:'h0, busy:'h0}, '{other_status:'h1832b6, wel:'h0, busy:'h0}}